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USB4_STATUS
列挙型メンバー 24
| 名前 | 10進 | 16進 |
|---|---|---|
| ErrConn | 0 | 0x0 |
| ErrLink | 1 | 0x1 |
| ErrAddr | 2 | 0x2 |
| ErrAdp | 4 | 0x4 |
| HpAck | 7 | 0x7 |
| ErrEnum | 8 | 0x8 |
| ErrNua | 9 | 0x9 |
| ErrLen | 11 | 0xB |
| ErrHec | 12 | 0xC |
| ErrFc | 13 | 0xD |
| ErrPlug | 14 | 0xE |
| ErrLock | 15 | 0xF |
| DpBw | 32 | 0x20 |
| RopCmplt | 33 | 0x21 |
| PopCmplt | 34 | 0x22 |
| PcieWake | 35 | 0x23 |
| DpConChange | 36 | 0x24 |
| DpTxDiscovery | 37 | 0x25 |
| LinkRecovery | 38 | 0x26 |
| AsymLink | 39 | 0x27 |
| PollingSkipped | 252 | 0xFC |
| PollingTimeout | 253 | 0xFD |
| StatusSuccess | 254 | 0xFE |
| StatusUnknown | 255 | 0xFF |
各言語での定義
列挙メンバーの定義。HSP タブは #define global(値は16進)。
typedef enum USB4_STATUS : int {
ErrConn = 0,
ErrLink = 1,
ErrAddr = 2,
ErrAdp = 4,
HpAck = 7,
ErrEnum = 8,
ErrNua = 9,
ErrLen = 11,
ErrHec = 12,
ErrFc = 13,
ErrPlug = 14,
ErrLock = 15,
DpBw = 32,
RopCmplt = 33,
PopCmplt = 34,
PcieWake = 35,
DpConChange = 36,
DpTxDiscovery = 37,
LinkRecovery = 38,
AsymLink = 39,
PollingSkipped = 252,
PollingTimeout = 253,
StatusSuccess = 254,
StatusUnknown = 255
} USB4_STATUS;public enum USB4_STATUS : int
{
ErrConn = 0,
ErrLink = 1,
ErrAddr = 2,
ErrAdp = 4,
HpAck = 7,
ErrEnum = 8,
ErrNua = 9,
ErrLen = 11,
ErrHec = 12,
ErrFc = 13,
ErrPlug = 14,
ErrLock = 15,
DpBw = 32,
RopCmplt = 33,
PopCmplt = 34,
PcieWake = 35,
DpConChange = 36,
DpTxDiscovery = 37,
LinkRecovery = 38,
AsymLink = 39,
PollingSkipped = 252,
PollingTimeout = 253,
StatusSuccess = 254,
StatusUnknown = 255,
}Public Enum USB4_STATUS As Integer
ErrConn = 0
ErrLink = 1
ErrAddr = 2
ErrAdp = 4
HpAck = 7
ErrEnum = 8
ErrNua = 9
ErrLen = 11
ErrHec = 12
ErrFc = 13
ErrPlug = 14
ErrLock = 15
DpBw = 32
RopCmplt = 33
PopCmplt = 34
PcieWake = 35
DpConChange = 36
DpTxDiscovery = 37
LinkRecovery = 38
AsymLink = 39
PollingSkipped = 252
PollingTimeout = 253
StatusSuccess = 254
StatusUnknown = 255
End Enumimport enum
class USB4_STATUS(enum.IntEnum):
ErrConn = 0
ErrLink = 1
ErrAddr = 2
ErrAdp = 4
HpAck = 7
ErrEnum = 8
ErrNua = 9
ErrLen = 11
ErrHec = 12
ErrFc = 13
ErrPlug = 14
ErrLock = 15
DpBw = 32
RopCmplt = 33
PopCmplt = 34
PcieWake = 35
DpConChange = 36
DpTxDiscovery = 37
LinkRecovery = 38
AsymLink = 39
PollingSkipped = 252
PollingTimeout = 253
StatusSuccess = 254
StatusUnknown = 255// USB4_STATUS
pub const ErrConn: i32 = 0;
pub const ErrLink: i32 = 1;
pub const ErrAddr: i32 = 2;
pub const ErrAdp: i32 = 4;
pub const HpAck: i32 = 7;
pub const ErrEnum: i32 = 8;
pub const ErrNua: i32 = 9;
pub const ErrLen: i32 = 11;
pub const ErrHec: i32 = 12;
pub const ErrFc: i32 = 13;
pub const ErrPlug: i32 = 14;
pub const ErrLock: i32 = 15;
pub const DpBw: i32 = 32;
pub const RopCmplt: i32 = 33;
pub const PopCmplt: i32 = 34;
pub const PcieWake: i32 = 35;
pub const DpConChange: i32 = 36;
pub const DpTxDiscovery: i32 = 37;
pub const LinkRecovery: i32 = 38;
pub const AsymLink: i32 = 39;
pub const PollingSkipped: i32 = 252;
pub const PollingTimeout: i32 = 253;
pub const StatusSuccess: i32 = 254;
pub const StatusUnknown: i32 = 255;// USB4_STATUS
const (
ErrConn int32 = 0
ErrLink int32 = 1
ErrAddr int32 = 2
ErrAdp int32 = 4
HpAck int32 = 7
ErrEnum int32 = 8
ErrNua int32 = 9
ErrLen int32 = 11
ErrHec int32 = 12
ErrFc int32 = 13
ErrPlug int32 = 14
ErrLock int32 = 15
DpBw int32 = 32
RopCmplt int32 = 33
PopCmplt int32 = 34
PcieWake int32 = 35
DpConChange int32 = 36
DpTxDiscovery int32 = 37
LinkRecovery int32 = 38
AsymLink int32 = 39
PollingSkipped int32 = 252
PollingTimeout int32 = 253
StatusSuccess int32 = 254
StatusUnknown int32 = 255
)const
ErrConn = 0;
ErrLink = 1;
ErrAddr = 2;
ErrAdp = 4;
HpAck = 7;
ErrEnum = 8;
ErrNua = 9;
ErrLen = 11;
ErrHec = 12;
ErrFc = 13;
ErrPlug = 14;
ErrLock = 15;
DpBw = 32;
RopCmplt = 33;
PopCmplt = 34;
PcieWake = 35;
DpConChange = 36;
DpTxDiscovery = 37;
LinkRecovery = 38;
AsymLink = 39;
PollingSkipped = 252;
PollingTimeout = 253;
StatusSuccess = 254;
StatusUnknown = 255;// USB4_STATUS
pub const ErrConn: i32 = 0;
pub const ErrLink: i32 = 1;
pub const ErrAddr: i32 = 2;
pub const ErrAdp: i32 = 4;
pub const HpAck: i32 = 7;
pub const ErrEnum: i32 = 8;
pub const ErrNua: i32 = 9;
pub const ErrLen: i32 = 11;
pub const ErrHec: i32 = 12;
pub const ErrFc: i32 = 13;
pub const ErrPlug: i32 = 14;
pub const ErrLock: i32 = 15;
pub const DpBw: i32 = 32;
pub const RopCmplt: i32 = 33;
pub const PopCmplt: i32 = 34;
pub const PcieWake: i32 = 35;
pub const DpConChange: i32 = 36;
pub const DpTxDiscovery: i32 = 37;
pub const LinkRecovery: i32 = 38;
pub const AsymLink: i32 = 39;
pub const PollingSkipped: i32 = 252;
pub const PollingTimeout: i32 = 253;
pub const StatusSuccess: i32 = 254;
pub const StatusUnknown: i32 = 255;const
ErrConn* = 0
ErrLink* = 1
ErrAddr* = 2
ErrAdp* = 4
HpAck* = 7
ErrEnum* = 8
ErrNua* = 9
ErrLen* = 11
ErrHec* = 12
ErrFc* = 13
ErrPlug* = 14
ErrLock* = 15
DpBw* = 32
RopCmplt* = 33
PopCmplt* = 34
PcieWake* = 35
DpConChange* = 36
DpTxDiscovery* = 37
LinkRecovery* = 38
AsymLink* = 39
PollingSkipped* = 252
PollingTimeout* = 253
StatusSuccess* = 254
StatusUnknown* = 255enum USB4_STATUS : int {
ErrConn = 0,
ErrLink = 1,
ErrAddr = 2,
ErrAdp = 4,
HpAck = 7,
ErrEnum = 8,
ErrNua = 9,
ErrLen = 11,
ErrHec = 12,
ErrFc = 13,
ErrPlug = 14,
ErrLock = 15,
DpBw = 32,
RopCmplt = 33,
PopCmplt = 34,
PcieWake = 35,
DpConChange = 36,
DpTxDiscovery = 37,
LinkRecovery = 38,
AsymLink = 39,
PollingSkipped = 252,
PollingTimeout = 253,
StatusSuccess = 254,
StatusUnknown = 255,
}#define global ErrConn 0x0
#define global ErrLink 0x1
#define global ErrAddr 0x2
#define global ErrAdp 0x4
#define global HpAck 0x7
#define global ErrEnum 0x8
#define global ErrNua 0x9
#define global ErrLen 0xB
#define global ErrHec 0xC
#define global ErrFc 0xD
#define global ErrPlug 0xE
#define global ErrLock 0xF
#define global DpBw 0x20
#define global RopCmplt 0x21
#define global PopCmplt 0x22
#define global PcieWake 0x23
#define global DpConChange 0x24
#define global DpTxDiscovery 0x25
#define global LinkRecovery 0x26
#define global AsymLink 0x27
#define global PollingSkipped 0xFC
#define global PollingTimeout 0xFD
#define global StatusSuccess 0xFE
#define global StatusUnknown 0xFF