ホーム › NetworkManagement.WiFi › DEVPROP_PCIROOTBUS_SECONDARYINTERFACE

DEVPROP_PCIROOTBUS_SECONDARYINTERFACE

列挙型

基底型u4

メンバー 4

名前	10進	16進
DevProp_PciRootBus_SecondaryInterface_PciConventional	0	0x0
DevProp_PciRootBus_SecondaryInterface_PciXMode1	1	0x1
DevProp_PciRootBus_SecondaryInterface_PciXMode2	2	0x2
DevProp_PciRootBus_SecondaryInterface_PciExpress	3	0x3

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum DEVPROP_PCIROOTBUS_SECONDARYINTERFACE : unsigned int {
    DevProp_PciRootBus_SecondaryInterface_PciConventional = 0,
    DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1,
    DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2,
    DevProp_PciRootBus_SecondaryInterface_PciExpress = 3
} DEVPROP_PCIROOTBUS_SECONDARYINTERFACE;

public enum DEVPROP_PCIROOTBUS_SECONDARYINTERFACE : uint
{
    DevProp_PciRootBus_SecondaryInterface_PciConventional = 0,
    DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1,
    DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2,
    DevProp_PciRootBus_SecondaryInterface_PciExpress = 3,
}

Public Enum DEVPROP_PCIROOTBUS_SECONDARYINTERFACE As UInteger
    DevProp_PciRootBus_SecondaryInterface_PciConventional = 0
    DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1
    DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2
    DevProp_PciRootBus_SecondaryInterface_PciExpress = 3
End Enum

import enum

class DEVPROP_PCIROOTBUS_SECONDARYINTERFACE(enum.IntEnum):
    DevProp_PciRootBus_SecondaryInterface_PciConventional = 0
    DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1
    DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2
    DevProp_PciRootBus_SecondaryInterface_PciExpress = 3

// DEVPROP_PCIROOTBUS_SECONDARYINTERFACE
pub const DevProp_PciRootBus_SecondaryInterface_PciConventional: u32 = 0;
pub const DevProp_PciRootBus_SecondaryInterface_PciXMode1: u32 = 1;
pub const DevProp_PciRootBus_SecondaryInterface_PciXMode2: u32 = 2;
pub const DevProp_PciRootBus_SecondaryInterface_PciExpress: u32 = 3;

// DEVPROP_PCIROOTBUS_SECONDARYINTERFACE
const (
	DevProp_PciRootBus_SecondaryInterface_PciConventional uint32 = 0
	DevProp_PciRootBus_SecondaryInterface_PciXMode1 uint32 = 1
	DevProp_PciRootBus_SecondaryInterface_PciXMode2 uint32 = 2
	DevProp_PciRootBus_SecondaryInterface_PciExpress uint32 = 3
)

const
  DevProp_PciRootBus_SecondaryInterface_PciConventional = 0;
  DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1;
  DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2;
  DevProp_PciRootBus_SecondaryInterface_PciExpress = 3;

// DEVPROP_PCIROOTBUS_SECONDARYINTERFACE
pub const DevProp_PciRootBus_SecondaryInterface_PciConventional: u32 = 0;
pub const DevProp_PciRootBus_SecondaryInterface_PciXMode1: u32 = 1;
pub const DevProp_PciRootBus_SecondaryInterface_PciXMode2: u32 = 2;
pub const DevProp_PciRootBus_SecondaryInterface_PciExpress: u32 = 3;

const
  DevProp_PciRootBus_SecondaryInterface_PciConventional* = 0
  DevProp_PciRootBus_SecondaryInterface_PciXMode1* = 1
  DevProp_PciRootBus_SecondaryInterface_PciXMode2* = 2
  DevProp_PciRootBus_SecondaryInterface_PciExpress* = 3

enum DEVPROP_PCIROOTBUS_SECONDARYINTERFACE : uint {
    DevProp_PciRootBus_SecondaryInterface_PciConventional = 0,
    DevProp_PciRootBus_SecondaryInterface_PciXMode1 = 1,
    DevProp_PciRootBus_SecondaryInterface_PciXMode2 = 2,
    DevProp_PciRootBus_SecondaryInterface_PciExpress = 3,
}

#define global DevProp_PciRootBus_SecondaryInterface_PciConventional 0x0
#define global DevProp_PciRootBus_SecondaryInterface_PciXMode1       0x1
#define global DevProp_PciRootBus_SecondaryInterface_PciXMode2       0x2
#define global DevProp_PciRootBus_SecondaryInterface_PciExpress      0x3