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NVME_ACCESS_FREQUENCIES

列挙型

基底型i4

メンバー 9

名前	10進	16進
NVME_ACCESS_FREQUENCY_NONE	0	0x0
NVME_ACCESS_FREQUENCY_TYPICAL	1	0x1
NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ	2	0x2
NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ	3	0x3
NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ	4	0x4
NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ	5	0x5
NVME_ACCESS_FREQUENCY_ONE_TIME_READ	6	0x6
NVME_ACCESS_FREQUENCY_SPECULATIVE_READ	7	0x7
NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN	8	0x8

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum NVME_ACCESS_FREQUENCIES : int {
    NVME_ACCESS_FREQUENCY_NONE = 0,
    NVME_ACCESS_FREQUENCY_TYPICAL = 1,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3,
    NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4,
    NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5,
    NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6,
    NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7,
    NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8
} NVME_ACCESS_FREQUENCIES;

public enum NVME_ACCESS_FREQUENCIES : int
{
    NVME_ACCESS_FREQUENCY_NONE = 0,
    NVME_ACCESS_FREQUENCY_TYPICAL = 1,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3,
    NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4,
    NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5,
    NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6,
    NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7,
    NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8,
}

Public Enum NVME_ACCESS_FREQUENCIES As Integer
    NVME_ACCESS_FREQUENCY_NONE = 0
    NVME_ACCESS_FREQUENCY_TYPICAL = 1
    NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2
    NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3
    NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4
    NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5
    NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6
    NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7
    NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8
End Enum

import enum

class NVME_ACCESS_FREQUENCIES(enum.IntEnum):
    NVME_ACCESS_FREQUENCY_NONE = 0
    NVME_ACCESS_FREQUENCY_TYPICAL = 1
    NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2
    NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3
    NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4
    NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5
    NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6
    NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7
    NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8

// NVME_ACCESS_FREQUENCIES
pub const NVME_ACCESS_FREQUENCY_NONE: i32 = 0;
pub const NVME_ACCESS_FREQUENCY_TYPICAL: i32 = 1;
pub const NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ: i32 = 2;
pub const NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ: i32 = 3;
pub const NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ: i32 = 4;
pub const NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ: i32 = 5;
pub const NVME_ACCESS_FREQUENCY_ONE_TIME_READ: i32 = 6;
pub const NVME_ACCESS_FREQUENCY_SPECULATIVE_READ: i32 = 7;
pub const NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN: i32 = 8;

// NVME_ACCESS_FREQUENCIES
const (
	NVME_ACCESS_FREQUENCY_NONE int32 = 0
	NVME_ACCESS_FREQUENCY_TYPICAL int32 = 1
	NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ int32 = 2
	NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ int32 = 3
	NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ int32 = 4
	NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ int32 = 5
	NVME_ACCESS_FREQUENCY_ONE_TIME_READ int32 = 6
	NVME_ACCESS_FREQUENCY_SPECULATIVE_READ int32 = 7
	NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN int32 = 8
)

const
  NVME_ACCESS_FREQUENCY_NONE = 0;
  NVME_ACCESS_FREQUENCY_TYPICAL = 1;
  NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2;
  NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3;
  NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4;
  NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5;
  NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6;
  NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7;
  NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8;

// NVME_ACCESS_FREQUENCIES
pub const NVME_ACCESS_FREQUENCY_NONE: i32 = 0;
pub const NVME_ACCESS_FREQUENCY_TYPICAL: i32 = 1;
pub const NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ: i32 = 2;
pub const NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ: i32 = 3;
pub const NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ: i32 = 4;
pub const NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ: i32 = 5;
pub const NVME_ACCESS_FREQUENCY_ONE_TIME_READ: i32 = 6;
pub const NVME_ACCESS_FREQUENCY_SPECULATIVE_READ: i32 = 7;
pub const NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN: i32 = 8;

const
  NVME_ACCESS_FREQUENCY_NONE* = 0
  NVME_ACCESS_FREQUENCY_TYPICAL* = 1
  NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ* = 2
  NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ* = 3
  NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ* = 4
  NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ* = 5
  NVME_ACCESS_FREQUENCY_ONE_TIME_READ* = 6
  NVME_ACCESS_FREQUENCY_SPECULATIVE_READ* = 7
  NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN* = 8

enum NVME_ACCESS_FREQUENCIES : int {
    NVME_ACCESS_FREQUENCY_NONE = 0,
    NVME_ACCESS_FREQUENCY_TYPICAL = 1,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ = 2,
    NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ = 3,
    NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ = 4,
    NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ = 5,
    NVME_ACCESS_FREQUENCY_ONE_TIME_READ = 6,
    NVME_ACCESS_FREQUENCY_SPECULATIVE_READ = 7,
    NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN = 8,
}

#define global NVME_ACCESS_FREQUENCY_NONE                 0x0
#define global NVME_ACCESS_FREQUENCY_TYPICAL              0x1
#define global NVME_ACCESS_FREQUENCY_INFR_WRITE_INFR_READ 0x2
#define global NVME_ACCESS_FREQUENCY_INFR_WRITE_FR_READ   0x3
#define global NVME_ACCESS_FREQUENCY_FR_WRITE_INFR_READ   0x4
#define global NVME_ACCESS_FREQUENCY_FR_WRITE_FR_READ     0x5
#define global NVME_ACCESS_FREQUENCY_ONE_TIME_READ        0x6
#define global NVME_ACCESS_FREQUENCY_SPECULATIVE_READ     0x7
#define global NVME_ACCESS_FREQUENCY_WILL_BE_OVERWRITTEN  0x8