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NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS

列挙型

基底型i4

メンバー 3

名前	10進	16進
NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS	1	0x1
NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS	2	0x2
NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES	3	0x3

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS : int {
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3
} NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS;

public enum NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS : int
{
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3,
}

Public Enum NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS As Integer
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3
End Enum

import enum

class NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS(enum.IntEnum):
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3

// NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS: i32 = 1;
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS: i32 = 2;
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES: i32 = 3;

// NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS
const (
	NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS int32 = 1
	NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS int32 = 2
	NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES int32 = 3
)

const
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1;
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2;
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3;

// NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS: i32 = 1;
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS: i32 = 2;
pub const NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES: i32 = 3;

const
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS* = 1
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS* = 2
  NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES* = 3

enum NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATIONS : int {
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS = 1,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS = 2,
    NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES = 3,
}

#define global NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_RETURN_PARAMETERS  0x1
#define global NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_GET_STATUS         0x2
#define global NVME_DIRECTIVE_RECEIVE_STREAMS_OPERATION_ALLOCATE_RESOURCES 0x3