NVME_NVM_COMMANDS

列挙型

基底型i4

メンバー 16

名前	10進	16進
NVME_NVM_COMMAND_FLUSH	0	0x0
NVME_NVM_COMMAND_WRITE	1	0x1
NVME_NVM_COMMAND_READ	2	0x2
NVME_NVM_COMMAND_WRITE_UNCORRECTABLE	4	0x4
NVME_NVM_COMMAND_COMPARE	5	0x5
NVME_NVM_COMMAND_WRITE_ZEROES	8	0x8
NVME_NVM_COMMAND_DATASET_MANAGEMENT	9	0x9
NVME_NVM_COMMAND_VERIFY	12	0xC
NVME_NVM_COMMAND_RESERVATION_REGISTER	13	0xD
NVME_NVM_COMMAND_RESERVATION_REPORT	14	0xE
NVME_NVM_COMMAND_RESERVATION_ACQUIRE	17	0x11
NVME_NVM_COMMAND_RESERVATION_RELEASE	21	0x15
NVME_NVM_COMMAND_COPY	25	0x19
NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND	121	0x79
NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE	122	0x7A
NVME_NVM_COMMAND_ZONE_APPEND	125	0x7D

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum NVME_NVM_COMMANDS : int {
    NVME_NVM_COMMAND_FLUSH = 0,
    NVME_NVM_COMMAND_WRITE = 1,
    NVME_NVM_COMMAND_READ = 2,
    NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4,
    NVME_NVM_COMMAND_COMPARE = 5,
    NVME_NVM_COMMAND_WRITE_ZEROES = 8,
    NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9,
    NVME_NVM_COMMAND_VERIFY = 12,
    NVME_NVM_COMMAND_RESERVATION_REGISTER = 13,
    NVME_NVM_COMMAND_RESERVATION_REPORT = 14,
    NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17,
    NVME_NVM_COMMAND_RESERVATION_RELEASE = 21,
    NVME_NVM_COMMAND_COPY = 25,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122,
    NVME_NVM_COMMAND_ZONE_APPEND = 125
} NVME_NVM_COMMANDS;

public enum NVME_NVM_COMMANDS : int
{
    NVME_NVM_COMMAND_FLUSH = 0,
    NVME_NVM_COMMAND_WRITE = 1,
    NVME_NVM_COMMAND_READ = 2,
    NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4,
    NVME_NVM_COMMAND_COMPARE = 5,
    NVME_NVM_COMMAND_WRITE_ZEROES = 8,
    NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9,
    NVME_NVM_COMMAND_VERIFY = 12,
    NVME_NVM_COMMAND_RESERVATION_REGISTER = 13,
    NVME_NVM_COMMAND_RESERVATION_REPORT = 14,
    NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17,
    NVME_NVM_COMMAND_RESERVATION_RELEASE = 21,
    NVME_NVM_COMMAND_COPY = 25,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122,
    NVME_NVM_COMMAND_ZONE_APPEND = 125,
}

Public Enum NVME_NVM_COMMANDS As Integer
    NVME_NVM_COMMAND_FLUSH = 0
    NVME_NVM_COMMAND_WRITE = 1
    NVME_NVM_COMMAND_READ = 2
    NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4
    NVME_NVM_COMMAND_COMPARE = 5
    NVME_NVM_COMMAND_WRITE_ZEROES = 8
    NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9
    NVME_NVM_COMMAND_VERIFY = 12
    NVME_NVM_COMMAND_RESERVATION_REGISTER = 13
    NVME_NVM_COMMAND_RESERVATION_REPORT = 14
    NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17
    NVME_NVM_COMMAND_RESERVATION_RELEASE = 21
    NVME_NVM_COMMAND_COPY = 25
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122
    NVME_NVM_COMMAND_ZONE_APPEND = 125
End Enum

import enum

class NVME_NVM_COMMANDS(enum.IntEnum):
    NVME_NVM_COMMAND_FLUSH = 0
    NVME_NVM_COMMAND_WRITE = 1
    NVME_NVM_COMMAND_READ = 2
    NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4
    NVME_NVM_COMMAND_COMPARE = 5
    NVME_NVM_COMMAND_WRITE_ZEROES = 8
    NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9
    NVME_NVM_COMMAND_VERIFY = 12
    NVME_NVM_COMMAND_RESERVATION_REGISTER = 13
    NVME_NVM_COMMAND_RESERVATION_REPORT = 14
    NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17
    NVME_NVM_COMMAND_RESERVATION_RELEASE = 21
    NVME_NVM_COMMAND_COPY = 25
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122
    NVME_NVM_COMMAND_ZONE_APPEND = 125

// NVME_NVM_COMMANDS
pub const NVME_NVM_COMMAND_FLUSH: i32 = 0;
pub const NVME_NVM_COMMAND_WRITE: i32 = 1;
pub const NVME_NVM_COMMAND_READ: i32 = 2;
pub const NVME_NVM_COMMAND_WRITE_UNCORRECTABLE: i32 = 4;
pub const NVME_NVM_COMMAND_COMPARE: i32 = 5;
pub const NVME_NVM_COMMAND_WRITE_ZEROES: i32 = 8;
pub const NVME_NVM_COMMAND_DATASET_MANAGEMENT: i32 = 9;
pub const NVME_NVM_COMMAND_VERIFY: i32 = 12;
pub const NVME_NVM_COMMAND_RESERVATION_REGISTER: i32 = 13;
pub const NVME_NVM_COMMAND_RESERVATION_REPORT: i32 = 14;
pub const NVME_NVM_COMMAND_RESERVATION_ACQUIRE: i32 = 17;
pub const NVME_NVM_COMMAND_RESERVATION_RELEASE: i32 = 21;
pub const NVME_NVM_COMMAND_COPY: i32 = 25;
pub const NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND: i32 = 121;
pub const NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE: i32 = 122;
pub const NVME_NVM_COMMAND_ZONE_APPEND: i32 = 125;

// NVME_NVM_COMMANDS
const (
	NVME_NVM_COMMAND_FLUSH int32 = 0
	NVME_NVM_COMMAND_WRITE int32 = 1
	NVME_NVM_COMMAND_READ int32 = 2
	NVME_NVM_COMMAND_WRITE_UNCORRECTABLE int32 = 4
	NVME_NVM_COMMAND_COMPARE int32 = 5
	NVME_NVM_COMMAND_WRITE_ZEROES int32 = 8
	NVME_NVM_COMMAND_DATASET_MANAGEMENT int32 = 9
	NVME_NVM_COMMAND_VERIFY int32 = 12
	NVME_NVM_COMMAND_RESERVATION_REGISTER int32 = 13
	NVME_NVM_COMMAND_RESERVATION_REPORT int32 = 14
	NVME_NVM_COMMAND_RESERVATION_ACQUIRE int32 = 17
	NVME_NVM_COMMAND_RESERVATION_RELEASE int32 = 21
	NVME_NVM_COMMAND_COPY int32 = 25
	NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND int32 = 121
	NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE int32 = 122
	NVME_NVM_COMMAND_ZONE_APPEND int32 = 125
)

const
  NVME_NVM_COMMAND_FLUSH = 0;
  NVME_NVM_COMMAND_WRITE = 1;
  NVME_NVM_COMMAND_READ = 2;
  NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4;
  NVME_NVM_COMMAND_COMPARE = 5;
  NVME_NVM_COMMAND_WRITE_ZEROES = 8;
  NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9;
  NVME_NVM_COMMAND_VERIFY = 12;
  NVME_NVM_COMMAND_RESERVATION_REGISTER = 13;
  NVME_NVM_COMMAND_RESERVATION_REPORT = 14;
  NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17;
  NVME_NVM_COMMAND_RESERVATION_RELEASE = 21;
  NVME_NVM_COMMAND_COPY = 25;
  NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121;
  NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122;
  NVME_NVM_COMMAND_ZONE_APPEND = 125;

// NVME_NVM_COMMANDS
pub const NVME_NVM_COMMAND_FLUSH: i32 = 0;
pub const NVME_NVM_COMMAND_WRITE: i32 = 1;
pub const NVME_NVM_COMMAND_READ: i32 = 2;
pub const NVME_NVM_COMMAND_WRITE_UNCORRECTABLE: i32 = 4;
pub const NVME_NVM_COMMAND_COMPARE: i32 = 5;
pub const NVME_NVM_COMMAND_WRITE_ZEROES: i32 = 8;
pub const NVME_NVM_COMMAND_DATASET_MANAGEMENT: i32 = 9;
pub const NVME_NVM_COMMAND_VERIFY: i32 = 12;
pub const NVME_NVM_COMMAND_RESERVATION_REGISTER: i32 = 13;
pub const NVME_NVM_COMMAND_RESERVATION_REPORT: i32 = 14;
pub const NVME_NVM_COMMAND_RESERVATION_ACQUIRE: i32 = 17;
pub const NVME_NVM_COMMAND_RESERVATION_RELEASE: i32 = 21;
pub const NVME_NVM_COMMAND_COPY: i32 = 25;
pub const NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND: i32 = 121;
pub const NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE: i32 = 122;
pub const NVME_NVM_COMMAND_ZONE_APPEND: i32 = 125;

const
  NVME_NVM_COMMAND_FLUSH* = 0
  NVME_NVM_COMMAND_WRITE* = 1
  NVME_NVM_COMMAND_READ* = 2
  NVME_NVM_COMMAND_WRITE_UNCORRECTABLE* = 4
  NVME_NVM_COMMAND_COMPARE* = 5
  NVME_NVM_COMMAND_WRITE_ZEROES* = 8
  NVME_NVM_COMMAND_DATASET_MANAGEMENT* = 9
  NVME_NVM_COMMAND_VERIFY* = 12
  NVME_NVM_COMMAND_RESERVATION_REGISTER* = 13
  NVME_NVM_COMMAND_RESERVATION_REPORT* = 14
  NVME_NVM_COMMAND_RESERVATION_ACQUIRE* = 17
  NVME_NVM_COMMAND_RESERVATION_RELEASE* = 21
  NVME_NVM_COMMAND_COPY* = 25
  NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND* = 121
  NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE* = 122
  NVME_NVM_COMMAND_ZONE_APPEND* = 125

enum NVME_NVM_COMMANDS : int {
    NVME_NVM_COMMAND_FLUSH = 0,
    NVME_NVM_COMMAND_WRITE = 1,
    NVME_NVM_COMMAND_READ = 2,
    NVME_NVM_COMMAND_WRITE_UNCORRECTABLE = 4,
    NVME_NVM_COMMAND_COMPARE = 5,
    NVME_NVM_COMMAND_WRITE_ZEROES = 8,
    NVME_NVM_COMMAND_DATASET_MANAGEMENT = 9,
    NVME_NVM_COMMAND_VERIFY = 12,
    NVME_NVM_COMMAND_RESERVATION_REGISTER = 13,
    NVME_NVM_COMMAND_RESERVATION_REPORT = 14,
    NVME_NVM_COMMAND_RESERVATION_ACQUIRE = 17,
    NVME_NVM_COMMAND_RESERVATION_RELEASE = 21,
    NVME_NVM_COMMAND_COPY = 25,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND = 121,
    NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE = 122,
    NVME_NVM_COMMAND_ZONE_APPEND = 125,
}

#define global NVME_NVM_COMMAND_FLUSH                   0x0
#define global NVME_NVM_COMMAND_WRITE                   0x1
#define global NVME_NVM_COMMAND_READ                    0x2
#define global NVME_NVM_COMMAND_WRITE_UNCORRECTABLE     0x4
#define global NVME_NVM_COMMAND_COMPARE                 0x5
#define global NVME_NVM_COMMAND_WRITE_ZEROES            0x8
#define global NVME_NVM_COMMAND_DATASET_MANAGEMENT      0x9
#define global NVME_NVM_COMMAND_VERIFY                  0xC
#define global NVME_NVM_COMMAND_RESERVATION_REGISTER    0xD
#define global NVME_NVM_COMMAND_RESERVATION_REPORT      0xE
#define global NVME_NVM_COMMAND_RESERVATION_ACQUIRE     0x11
#define global NVME_NVM_COMMAND_RESERVATION_RELEASE     0x15
#define global NVME_NVM_COMMAND_COPY                    0x19
#define global NVME_NVM_COMMAND_ZONE_MANAGEMENT_SEND    0x79
#define global NVME_NVM_COMMAND_ZONE_MANAGEMENT_RECEIVE 0x7A
#define global NVME_NVM_COMMAND_ZONE_APPEND             0x7D