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NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES

列挙型

基底型i4

メンバー 4

名前	10進	16進
NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE	0	0x0
NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED	1	0x1
NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0	2	0x2
NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1	3	0x3

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES : int {
    NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0,
    NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3
} NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES;

public enum NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES : int
{
    NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0,
    NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3,
}

Public Enum NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES As Integer
    NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0
    NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3
End Enum

import enum

class NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES(enum.IntEnum):
    NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0
    NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3

// NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE: i32 = 0;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED: i32 = 1;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0: i32 = 2;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1: i32 = 3;

// NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES
const (
	NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE int32 = 0
	NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED int32 = 1
	NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 int32 = 2
	NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 int32 = 3
)

const
  NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0;
  NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1;
  NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2;
  NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3;

// NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE: i32 = 0;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED: i32 = 1;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0: i32 = 2;
pub const NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1: i32 = 3;

const
  NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE* = 0
  NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED* = 1
  NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0* = 2
  NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1* = 3

enum NVME_RESERVATION_REGISTER_PTPL_STATE_CHANGES : int {
    NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE = 0,
    NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED = 1,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0 = 2,
    NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1 = 3,
}

#define global NVME_RESERVATION_REGISTER_PTPL_STATE_NO_CHANGE 0x0
#define global NVME_RESERVATION_REGISTER_PTPL_STATE_RESERVED  0x1
#define global NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_0  0x2
#define global NVME_RESERVATION_REGISTER_PTPL_STATE_SET_TO_1  0x3