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NVME_ZONE_RECEIVE_ACTION_SPECIFIC

列挙型
基底型i4

メンバー 8

名前10進16進
NVME_ZRA_ALL_ZONES00x0
NVME_ZRA_EMPTY_STATE_ZONES10x1
NVME_ZRA_IO_STATE_ZONES20x2
NVME_ZRA_EO_STATE_ZONES30x3
NVME_ZRA_CLOSED_STATE_ZONES40x4
NVME_ZRA_FULL_STATE_ZONES50x5
NVME_ZRA_RO_STATE_ZONES60x6
NVME_ZRA_OFFLINE_STATE_ZONES70x7

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum NVME_ZONE_RECEIVE_ACTION_SPECIFIC : int {
    NVME_ZRA_ALL_ZONES = 0,
    NVME_ZRA_EMPTY_STATE_ZONES = 1,
    NVME_ZRA_IO_STATE_ZONES = 2,
    NVME_ZRA_EO_STATE_ZONES = 3,
    NVME_ZRA_CLOSED_STATE_ZONES = 4,
    NVME_ZRA_FULL_STATE_ZONES = 5,
    NVME_ZRA_RO_STATE_ZONES = 6,
    NVME_ZRA_OFFLINE_STATE_ZONES = 7
} NVME_ZONE_RECEIVE_ACTION_SPECIFIC;
public enum NVME_ZONE_RECEIVE_ACTION_SPECIFIC : int
{
    NVME_ZRA_ALL_ZONES = 0,
    NVME_ZRA_EMPTY_STATE_ZONES = 1,
    NVME_ZRA_IO_STATE_ZONES = 2,
    NVME_ZRA_EO_STATE_ZONES = 3,
    NVME_ZRA_CLOSED_STATE_ZONES = 4,
    NVME_ZRA_FULL_STATE_ZONES = 5,
    NVME_ZRA_RO_STATE_ZONES = 6,
    NVME_ZRA_OFFLINE_STATE_ZONES = 7,
}
Public Enum NVME_ZONE_RECEIVE_ACTION_SPECIFIC As Integer
    NVME_ZRA_ALL_ZONES = 0
    NVME_ZRA_EMPTY_STATE_ZONES = 1
    NVME_ZRA_IO_STATE_ZONES = 2
    NVME_ZRA_EO_STATE_ZONES = 3
    NVME_ZRA_CLOSED_STATE_ZONES = 4
    NVME_ZRA_FULL_STATE_ZONES = 5
    NVME_ZRA_RO_STATE_ZONES = 6
    NVME_ZRA_OFFLINE_STATE_ZONES = 7
End Enum
import enum

class NVME_ZONE_RECEIVE_ACTION_SPECIFIC(enum.IntEnum):
    NVME_ZRA_ALL_ZONES = 0
    NVME_ZRA_EMPTY_STATE_ZONES = 1
    NVME_ZRA_IO_STATE_ZONES = 2
    NVME_ZRA_EO_STATE_ZONES = 3
    NVME_ZRA_CLOSED_STATE_ZONES = 4
    NVME_ZRA_FULL_STATE_ZONES = 5
    NVME_ZRA_RO_STATE_ZONES = 6
    NVME_ZRA_OFFLINE_STATE_ZONES = 7
// NVME_ZONE_RECEIVE_ACTION_SPECIFIC
pub const NVME_ZRA_ALL_ZONES: i32 = 0;
pub const NVME_ZRA_EMPTY_STATE_ZONES: i32 = 1;
pub const NVME_ZRA_IO_STATE_ZONES: i32 = 2;
pub const NVME_ZRA_EO_STATE_ZONES: i32 = 3;
pub const NVME_ZRA_CLOSED_STATE_ZONES: i32 = 4;
pub const NVME_ZRA_FULL_STATE_ZONES: i32 = 5;
pub const NVME_ZRA_RO_STATE_ZONES: i32 = 6;
pub const NVME_ZRA_OFFLINE_STATE_ZONES: i32 = 7;
// NVME_ZONE_RECEIVE_ACTION_SPECIFIC
const (
	NVME_ZRA_ALL_ZONES int32 = 0
	NVME_ZRA_EMPTY_STATE_ZONES int32 = 1
	NVME_ZRA_IO_STATE_ZONES int32 = 2
	NVME_ZRA_EO_STATE_ZONES int32 = 3
	NVME_ZRA_CLOSED_STATE_ZONES int32 = 4
	NVME_ZRA_FULL_STATE_ZONES int32 = 5
	NVME_ZRA_RO_STATE_ZONES int32 = 6
	NVME_ZRA_OFFLINE_STATE_ZONES int32 = 7
)
const
  NVME_ZRA_ALL_ZONES = 0;
  NVME_ZRA_EMPTY_STATE_ZONES = 1;
  NVME_ZRA_IO_STATE_ZONES = 2;
  NVME_ZRA_EO_STATE_ZONES = 3;
  NVME_ZRA_CLOSED_STATE_ZONES = 4;
  NVME_ZRA_FULL_STATE_ZONES = 5;
  NVME_ZRA_RO_STATE_ZONES = 6;
  NVME_ZRA_OFFLINE_STATE_ZONES = 7;
// NVME_ZONE_RECEIVE_ACTION_SPECIFIC
pub const NVME_ZRA_ALL_ZONES: i32 = 0;
pub const NVME_ZRA_EMPTY_STATE_ZONES: i32 = 1;
pub const NVME_ZRA_IO_STATE_ZONES: i32 = 2;
pub const NVME_ZRA_EO_STATE_ZONES: i32 = 3;
pub const NVME_ZRA_CLOSED_STATE_ZONES: i32 = 4;
pub const NVME_ZRA_FULL_STATE_ZONES: i32 = 5;
pub const NVME_ZRA_RO_STATE_ZONES: i32 = 6;
pub const NVME_ZRA_OFFLINE_STATE_ZONES: i32 = 7;
const
  NVME_ZRA_ALL_ZONES* = 0
  NVME_ZRA_EMPTY_STATE_ZONES* = 1
  NVME_ZRA_IO_STATE_ZONES* = 2
  NVME_ZRA_EO_STATE_ZONES* = 3
  NVME_ZRA_CLOSED_STATE_ZONES* = 4
  NVME_ZRA_FULL_STATE_ZONES* = 5
  NVME_ZRA_RO_STATE_ZONES* = 6
  NVME_ZRA_OFFLINE_STATE_ZONES* = 7
enum NVME_ZONE_RECEIVE_ACTION_SPECIFIC : int {
    NVME_ZRA_ALL_ZONES = 0,
    NVME_ZRA_EMPTY_STATE_ZONES = 1,
    NVME_ZRA_IO_STATE_ZONES = 2,
    NVME_ZRA_EO_STATE_ZONES = 3,
    NVME_ZRA_CLOSED_STATE_ZONES = 4,
    NVME_ZRA_FULL_STATE_ZONES = 5,
    NVME_ZRA_RO_STATE_ZONES = 6,
    NVME_ZRA_OFFLINE_STATE_ZONES = 7,
}
#define global NVME_ZRA_ALL_ZONES           0x0
#define global NVME_ZRA_EMPTY_STATE_ZONES   0x1
#define global NVME_ZRA_IO_STATE_ZONES      0x2
#define global NVME_ZRA_EO_STATE_ZONES      0x3
#define global NVME_ZRA_CLOSED_STATE_ZONES  0x4
#define global NVME_ZRA_FULL_STATE_ZONES    0x5
#define global NVME_ZRA_RO_STATE_ZONES      0x6
#define global NVME_ZRA_OFFLINE_STATE_ZONES 0x7