REGISTER_ID

列挙型

基底型i4

メンバー 159

名前	10進	16進
X64_RegisterRax	0	0x0
X64_RegisterRcx	1	0x1
X64_RegisterRdx	2	0x2
X64_RegisterRbx	3	0x3
X64_RegisterRsp	4	0x4
X64_RegisterRbp	5	0x5
X64_RegisterRsi	6	0x6
X64_RegisterRdi	7	0x7
X64_RegisterR8	8	0x8
X64_RegisterR9	9	0x9
X64_RegisterR10	10	0xA
X64_RegisterR11	11	0xB
X64_RegisterR12	12	0xC
X64_RegisterR13	13	0xD
X64_RegisterR14	14	0xE
X64_RegisterR15	15	0xF
X64_RegisterRip	16	0x10
X64_RegisterRFlags	17	0x11
X64_RegisterXmm0	18	0x12
X64_RegisterXmm1	19	0x13
X64_RegisterXmm2	20	0x14
X64_RegisterXmm3	21	0x15
X64_RegisterXmm4	22	0x16
X64_RegisterXmm5	23	0x17
X64_RegisterXmm6	24	0x18
X64_RegisterXmm7	25	0x19
X64_RegisterXmm8	26	0x1A
X64_RegisterXmm9	27	0x1B
X64_RegisterXmm10	28	0x1C
X64_RegisterXmm11	29	0x1D
X64_RegisterXmm12	30	0x1E
X64_RegisterXmm13	31	0x1F
X64_RegisterXmm14	32	0x20
X64_RegisterXmm15	33	0x21
X64_RegisterFpMmx0	34	0x22
X64_RegisterFpMmx1	35	0x23
X64_RegisterFpMmx2	36	0x24
X64_RegisterFpMmx3	37	0x25
X64_RegisterFpMmx4	38	0x26
X64_RegisterFpMmx5	39	0x27
X64_RegisterFpMmx6	40	0x28
X64_RegisterFpMmx7	41	0x29
X64_RegisterFpControlStatus	42	0x2A
X64_RegisterXmmControlStatus	43	0x2B
X64_RegisterCr0	44	0x2C
X64_RegisterCr2	45	0x2D
X64_RegisterCr3	46	0x2E
X64_RegisterCr4	47	0x2F
X64_RegisterCr8	48	0x30
X64_RegisterEfer	49	0x31
X64_RegisterDr0	50	0x32
X64_RegisterDr1	51	0x33
X64_RegisterDr2	52	0x34
X64_RegisterDr3	53	0x35
X64_RegisterDr6	54	0x36
X64_RegisterDr7	55	0x37
X64_RegisterEs	56	0x38
X64_RegisterCs	57	0x39
X64_RegisterSs	58	0x3A
X64_RegisterDs	59	0x3B
X64_RegisterFs	60	0x3C
X64_RegisterGs	61	0x3D
X64_RegisterLdtr	62	0x3E
X64_RegisterTr	63	0x3F
X64_RegisterIdtr	64	0x40
X64_RegisterGdtr	65	0x41
X64_RegisterMax	66	0x42
ARM64_RegisterX0	67	0x43
ARM64_RegisterX1	68	0x44
ARM64_RegisterX2	69	0x45
ARM64_RegisterX3	70	0x46
ARM64_RegisterX4	71	0x47
ARM64_RegisterX5	72	0x48
ARM64_RegisterX6	73	0x49
ARM64_RegisterX7	74	0x4A
ARM64_RegisterX8	75	0x4B
ARM64_RegisterX9	76	0x4C
ARM64_RegisterX10	77	0x4D
ARM64_RegisterX11	78	0x4E
ARM64_RegisterX12	79	0x4F
ARM64_RegisterX13	80	0x50
ARM64_RegisterX14	81	0x51
ARM64_RegisterX15	82	0x52
ARM64_RegisterX16	83	0x53
ARM64_RegisterX17	84	0x54
ARM64_RegisterX18	85	0x55
ARM64_RegisterX19	86	0x56
ARM64_RegisterX20	87	0x57
ARM64_RegisterX21	88	0x58
ARM64_RegisterX22	89	0x59
ARM64_RegisterX23	90	0x5A
ARM64_RegisterX24	91	0x5B
ARM64_RegisterX25	92	0x5C
ARM64_RegisterX26	93	0x5D
ARM64_RegisterX27	94	0x5E
ARM64_RegisterX28	95	0x5F
ARM64_RegisterXFp	96	0x60
ARM64_RegisterXLr	97	0x61
ARM64_RegisterPc	98	0x62
ARM64_RegisterSpEl0	99	0x63
ARM64_RegisterSpEl1	100	0x64
ARM64_RegisterCpsr	101	0x65
ARM64_RegisterQ0	102	0x66
ARM64_RegisterQ1	103	0x67
ARM64_RegisterQ2	104	0x68
ARM64_RegisterQ3	105	0x69
ARM64_RegisterQ4	106	0x6A
ARM64_RegisterQ5	107	0x6B
ARM64_RegisterQ6	108	0x6C
ARM64_RegisterQ7	109	0x6D
ARM64_RegisterQ8	110	0x6E
ARM64_RegisterQ9	111	0x6F
ARM64_RegisterQ10	112	0x70
ARM64_RegisterQ11	113	0x71
ARM64_RegisterQ12	114	0x72
ARM64_RegisterQ13	115	0x73
ARM64_RegisterQ14	116	0x74
ARM64_RegisterQ15	117	0x75
ARM64_RegisterQ16	118	0x76
ARM64_RegisterQ17	119	0x77
ARM64_RegisterQ18	120	0x78
ARM64_RegisterQ19	121	0x79
ARM64_RegisterQ20	122	0x7A
ARM64_RegisterQ21	123	0x7B
ARM64_RegisterQ22	124	0x7C
ARM64_RegisterQ23	125	0x7D
ARM64_RegisterQ24	126	0x7E
ARM64_RegisterQ25	127	0x7F
ARM64_RegisterQ26	128	0x80
ARM64_RegisterQ27	129	0x81
ARM64_RegisterQ28	130	0x82
ARM64_RegisterQ29	131	0x83
ARM64_RegisterQ30	132	0x84
ARM64_RegisterQ31	133	0x85
ARM64_RegisterFpStatus	134	0x86
ARM64_RegisterFpControl	135	0x87
ARM64_RegisterEsrEl1	136	0x88
ARM64_RegisterSpsrEl1	137	0x89
ARM64_RegisterFarEl1	138	0x8A
ARM64_RegisterParEl1	139	0x8B
ARM64_RegisterElrEl1	140	0x8C
ARM64_RegisterTtbr0El1	141	0x8D
ARM64_RegisterTtbr1El1	142	0x8E
ARM64_RegisterVbarEl1	143	0x8F
ARM64_RegisterSctlrEl1	144	0x90
ARM64_RegisterActlrEl1	145	0x91
ARM64_RegisterTcrEl1	146	0x92
ARM64_RegisterMairEl1	147	0x93
ARM64_RegisterAmairEl1	148	0x94
ARM64_RegisterTpidrEl0	149	0x95
ARM64_RegisterTpidrroEl0	150	0x96
ARM64_RegisterTpidrEl1	151	0x97
ARM64_RegisterContextIdrEl1	152	0x98
ARM64_RegisterCpacrEl1	153	0x99
ARM64_RegisterCsselrEl1	154	0x9A
ARM64_RegisterCntkctlEl1	155	0x9B
ARM64_RegisterCntvCvalEl0	156	0x9C
ARM64_RegisterCntvCtlEl0	157	0x9D
ARM64_RegisterMax	158	0x9E

各言語での定義

列挙メンバーの定義。HSP タブは #define global(値は16進)。

typedef enum REGISTER_ID : int {
    X64_RegisterRax = 0,
    X64_RegisterRcx = 1,
    X64_RegisterRdx = 2,
    X64_RegisterRbx = 3,
    X64_RegisterRsp = 4,
    X64_RegisterRbp = 5,
    X64_RegisterRsi = 6,
    X64_RegisterRdi = 7,
    X64_RegisterR8 = 8,
    X64_RegisterR9 = 9,
    X64_RegisterR10 = 10,
    X64_RegisterR11 = 11,
    X64_RegisterR12 = 12,
    X64_RegisterR13 = 13,
    X64_RegisterR14 = 14,
    X64_RegisterR15 = 15,
    X64_RegisterRip = 16,
    X64_RegisterRFlags = 17,
    X64_RegisterXmm0 = 18,
    X64_RegisterXmm1 = 19,
    X64_RegisterXmm2 = 20,
    X64_RegisterXmm3 = 21,
    X64_RegisterXmm4 = 22,
    X64_RegisterXmm5 = 23,
    X64_RegisterXmm6 = 24,
    X64_RegisterXmm7 = 25,
    X64_RegisterXmm8 = 26,
    X64_RegisterXmm9 = 27,
    X64_RegisterXmm10 = 28,
    X64_RegisterXmm11 = 29,
    X64_RegisterXmm12 = 30,
    X64_RegisterXmm13 = 31,
    X64_RegisterXmm14 = 32,
    X64_RegisterXmm15 = 33,
    X64_RegisterFpMmx0 = 34,
    X64_RegisterFpMmx1 = 35,
    X64_RegisterFpMmx2 = 36,
    X64_RegisterFpMmx3 = 37,
    X64_RegisterFpMmx4 = 38,
    X64_RegisterFpMmx5 = 39,
    X64_RegisterFpMmx6 = 40,
    X64_RegisterFpMmx7 = 41,
    X64_RegisterFpControlStatus = 42,
    X64_RegisterXmmControlStatus = 43,
    X64_RegisterCr0 = 44,
    X64_RegisterCr2 = 45,
    X64_RegisterCr3 = 46,
    X64_RegisterCr4 = 47,
    X64_RegisterCr8 = 48,
    X64_RegisterEfer = 49,
    X64_RegisterDr0 = 50,
    X64_RegisterDr1 = 51,
    X64_RegisterDr2 = 52,
    X64_RegisterDr3 = 53,
    X64_RegisterDr6 = 54,
    X64_RegisterDr7 = 55,
    X64_RegisterEs = 56,
    X64_RegisterCs = 57,
    X64_RegisterSs = 58,
    X64_RegisterDs = 59,
    X64_RegisterFs = 60,
    X64_RegisterGs = 61,
    X64_RegisterLdtr = 62,
    X64_RegisterTr = 63,
    X64_RegisterIdtr = 64,
    X64_RegisterGdtr = 65,
    X64_RegisterMax = 66,
    ARM64_RegisterX0 = 67,
    ARM64_RegisterX1 = 68,
    ARM64_RegisterX2 = 69,
    ARM64_RegisterX3 = 70,
    ARM64_RegisterX4 = 71,
    ARM64_RegisterX5 = 72,
    ARM64_RegisterX6 = 73,
    ARM64_RegisterX7 = 74,
    ARM64_RegisterX8 = 75,
    ARM64_RegisterX9 = 76,
    ARM64_RegisterX10 = 77,
    ARM64_RegisterX11 = 78,
    ARM64_RegisterX12 = 79,
    ARM64_RegisterX13 = 80,
    ARM64_RegisterX14 = 81,
    ARM64_RegisterX15 = 82,
    ARM64_RegisterX16 = 83,
    ARM64_RegisterX17 = 84,
    ARM64_RegisterX18 = 85,
    ARM64_RegisterX19 = 86,
    ARM64_RegisterX20 = 87,
    ARM64_RegisterX21 = 88,
    ARM64_RegisterX22 = 89,
    ARM64_RegisterX23 = 90,
    ARM64_RegisterX24 = 91,
    ARM64_RegisterX25 = 92,
    ARM64_RegisterX26 = 93,
    ARM64_RegisterX27 = 94,
    ARM64_RegisterX28 = 95,
    ARM64_RegisterXFp = 96,
    ARM64_RegisterXLr = 97,
    ARM64_RegisterPc = 98,
    ARM64_RegisterSpEl0 = 99,
    ARM64_RegisterSpEl1 = 100,
    ARM64_RegisterCpsr = 101,
    ARM64_RegisterQ0 = 102,
    ARM64_RegisterQ1 = 103,
    ARM64_RegisterQ2 = 104,
    ARM64_RegisterQ3 = 105,
    ARM64_RegisterQ4 = 106,
    ARM64_RegisterQ5 = 107,
    ARM64_RegisterQ6 = 108,
    ARM64_RegisterQ7 = 109,
    ARM64_RegisterQ8 = 110,
    ARM64_RegisterQ9 = 111,
    ARM64_RegisterQ10 = 112,
    ARM64_RegisterQ11 = 113,
    ARM64_RegisterQ12 = 114,
    ARM64_RegisterQ13 = 115,
    ARM64_RegisterQ14 = 116,
    ARM64_RegisterQ15 = 117,
    ARM64_RegisterQ16 = 118,
    ARM64_RegisterQ17 = 119,
    ARM64_RegisterQ18 = 120,
    ARM64_RegisterQ19 = 121,
    ARM64_RegisterQ20 = 122,
    ARM64_RegisterQ21 = 123,
    ARM64_RegisterQ22 = 124,
    ARM64_RegisterQ23 = 125,
    ARM64_RegisterQ24 = 126,
    ARM64_RegisterQ25 = 127,
    ARM64_RegisterQ26 = 128,
    ARM64_RegisterQ27 = 129,
    ARM64_RegisterQ28 = 130,
    ARM64_RegisterQ29 = 131,
    ARM64_RegisterQ30 = 132,
    ARM64_RegisterQ31 = 133,
    ARM64_RegisterFpStatus = 134,
    ARM64_RegisterFpControl = 135,
    ARM64_RegisterEsrEl1 = 136,
    ARM64_RegisterSpsrEl1 = 137,
    ARM64_RegisterFarEl1 = 138,
    ARM64_RegisterParEl1 = 139,
    ARM64_RegisterElrEl1 = 140,
    ARM64_RegisterTtbr0El1 = 141,
    ARM64_RegisterTtbr1El1 = 142,
    ARM64_RegisterVbarEl1 = 143,
    ARM64_RegisterSctlrEl1 = 144,
    ARM64_RegisterActlrEl1 = 145,
    ARM64_RegisterTcrEl1 = 146,
    ARM64_RegisterMairEl1 = 147,
    ARM64_RegisterAmairEl1 = 148,
    ARM64_RegisterTpidrEl0 = 149,
    ARM64_RegisterTpidrroEl0 = 150,
    ARM64_RegisterTpidrEl1 = 151,
    ARM64_RegisterContextIdrEl1 = 152,
    ARM64_RegisterCpacrEl1 = 153,
    ARM64_RegisterCsselrEl1 = 154,
    ARM64_RegisterCntkctlEl1 = 155,
    ARM64_RegisterCntvCvalEl0 = 156,
    ARM64_RegisterCntvCtlEl0 = 157,
    ARM64_RegisterMax = 158
} REGISTER_ID;

public enum REGISTER_ID : int
{
    X64_RegisterRax = 0,
    X64_RegisterRcx = 1,
    X64_RegisterRdx = 2,
    X64_RegisterRbx = 3,
    X64_RegisterRsp = 4,
    X64_RegisterRbp = 5,
    X64_RegisterRsi = 6,
    X64_RegisterRdi = 7,
    X64_RegisterR8 = 8,
    X64_RegisterR9 = 9,
    X64_RegisterR10 = 10,
    X64_RegisterR11 = 11,
    X64_RegisterR12 = 12,
    X64_RegisterR13 = 13,
    X64_RegisterR14 = 14,
    X64_RegisterR15 = 15,
    X64_RegisterRip = 16,
    X64_RegisterRFlags = 17,
    X64_RegisterXmm0 = 18,
    X64_RegisterXmm1 = 19,
    X64_RegisterXmm2 = 20,
    X64_RegisterXmm3 = 21,
    X64_RegisterXmm4 = 22,
    X64_RegisterXmm5 = 23,
    X64_RegisterXmm6 = 24,
    X64_RegisterXmm7 = 25,
    X64_RegisterXmm8 = 26,
    X64_RegisterXmm9 = 27,
    X64_RegisterXmm10 = 28,
    X64_RegisterXmm11 = 29,
    X64_RegisterXmm12 = 30,
    X64_RegisterXmm13 = 31,
    X64_RegisterXmm14 = 32,
    X64_RegisterXmm15 = 33,
    X64_RegisterFpMmx0 = 34,
    X64_RegisterFpMmx1 = 35,
    X64_RegisterFpMmx2 = 36,
    X64_RegisterFpMmx3 = 37,
    X64_RegisterFpMmx4 = 38,
    X64_RegisterFpMmx5 = 39,
    X64_RegisterFpMmx6 = 40,
    X64_RegisterFpMmx7 = 41,
    X64_RegisterFpControlStatus = 42,
    X64_RegisterXmmControlStatus = 43,
    X64_RegisterCr0 = 44,
    X64_RegisterCr2 = 45,
    X64_RegisterCr3 = 46,
    X64_RegisterCr4 = 47,
    X64_RegisterCr8 = 48,
    X64_RegisterEfer = 49,
    X64_RegisterDr0 = 50,
    X64_RegisterDr1 = 51,
    X64_RegisterDr2 = 52,
    X64_RegisterDr3 = 53,
    X64_RegisterDr6 = 54,
    X64_RegisterDr7 = 55,
    X64_RegisterEs = 56,
    X64_RegisterCs = 57,
    X64_RegisterSs = 58,
    X64_RegisterDs = 59,
    X64_RegisterFs = 60,
    X64_RegisterGs = 61,
    X64_RegisterLdtr = 62,
    X64_RegisterTr = 63,
    X64_RegisterIdtr = 64,
    X64_RegisterGdtr = 65,
    X64_RegisterMax = 66,
    ARM64_RegisterX0 = 67,
    ARM64_RegisterX1 = 68,
    ARM64_RegisterX2 = 69,
    ARM64_RegisterX3 = 70,
    ARM64_RegisterX4 = 71,
    ARM64_RegisterX5 = 72,
    ARM64_RegisterX6 = 73,
    ARM64_RegisterX7 = 74,
    ARM64_RegisterX8 = 75,
    ARM64_RegisterX9 = 76,
    ARM64_RegisterX10 = 77,
    ARM64_RegisterX11 = 78,
    ARM64_RegisterX12 = 79,
    ARM64_RegisterX13 = 80,
    ARM64_RegisterX14 = 81,
    ARM64_RegisterX15 = 82,
    ARM64_RegisterX16 = 83,
    ARM64_RegisterX17 = 84,
    ARM64_RegisterX18 = 85,
    ARM64_RegisterX19 = 86,
    ARM64_RegisterX20 = 87,
    ARM64_RegisterX21 = 88,
    ARM64_RegisterX22 = 89,
    ARM64_RegisterX23 = 90,
    ARM64_RegisterX24 = 91,
    ARM64_RegisterX25 = 92,
    ARM64_RegisterX26 = 93,
    ARM64_RegisterX27 = 94,
    ARM64_RegisterX28 = 95,
    ARM64_RegisterXFp = 96,
    ARM64_RegisterXLr = 97,
    ARM64_RegisterPc = 98,
    ARM64_RegisterSpEl0 = 99,
    ARM64_RegisterSpEl1 = 100,
    ARM64_RegisterCpsr = 101,
    ARM64_RegisterQ0 = 102,
    ARM64_RegisterQ1 = 103,
    ARM64_RegisterQ2 = 104,
    ARM64_RegisterQ3 = 105,
    ARM64_RegisterQ4 = 106,
    ARM64_RegisterQ5 = 107,
    ARM64_RegisterQ6 = 108,
    ARM64_RegisterQ7 = 109,
    ARM64_RegisterQ8 = 110,
    ARM64_RegisterQ9 = 111,
    ARM64_RegisterQ10 = 112,
    ARM64_RegisterQ11 = 113,
    ARM64_RegisterQ12 = 114,
    ARM64_RegisterQ13 = 115,
    ARM64_RegisterQ14 = 116,
    ARM64_RegisterQ15 = 117,
    ARM64_RegisterQ16 = 118,
    ARM64_RegisterQ17 = 119,
    ARM64_RegisterQ18 = 120,
    ARM64_RegisterQ19 = 121,
    ARM64_RegisterQ20 = 122,
    ARM64_RegisterQ21 = 123,
    ARM64_RegisterQ22 = 124,
    ARM64_RegisterQ23 = 125,
    ARM64_RegisterQ24 = 126,
    ARM64_RegisterQ25 = 127,
    ARM64_RegisterQ26 = 128,
    ARM64_RegisterQ27 = 129,
    ARM64_RegisterQ28 = 130,
    ARM64_RegisterQ29 = 131,
    ARM64_RegisterQ30 = 132,
    ARM64_RegisterQ31 = 133,
    ARM64_RegisterFpStatus = 134,
    ARM64_RegisterFpControl = 135,
    ARM64_RegisterEsrEl1 = 136,
    ARM64_RegisterSpsrEl1 = 137,
    ARM64_RegisterFarEl1 = 138,
    ARM64_RegisterParEl1 = 139,
    ARM64_RegisterElrEl1 = 140,
    ARM64_RegisterTtbr0El1 = 141,
    ARM64_RegisterTtbr1El1 = 142,
    ARM64_RegisterVbarEl1 = 143,
    ARM64_RegisterSctlrEl1 = 144,
    ARM64_RegisterActlrEl1 = 145,
    ARM64_RegisterTcrEl1 = 146,
    ARM64_RegisterMairEl1 = 147,
    ARM64_RegisterAmairEl1 = 148,
    ARM64_RegisterTpidrEl0 = 149,
    ARM64_RegisterTpidrroEl0 = 150,
    ARM64_RegisterTpidrEl1 = 151,
    ARM64_RegisterContextIdrEl1 = 152,
    ARM64_RegisterCpacrEl1 = 153,
    ARM64_RegisterCsselrEl1 = 154,
    ARM64_RegisterCntkctlEl1 = 155,
    ARM64_RegisterCntvCvalEl0 = 156,
    ARM64_RegisterCntvCtlEl0 = 157,
    ARM64_RegisterMax = 158,
}

Public Enum REGISTER_ID As Integer
    X64_RegisterRax = 0
    X64_RegisterRcx = 1
    X64_RegisterRdx = 2
    X64_RegisterRbx = 3
    X64_RegisterRsp = 4
    X64_RegisterRbp = 5
    X64_RegisterRsi = 6
    X64_RegisterRdi = 7
    X64_RegisterR8 = 8
    X64_RegisterR9 = 9
    X64_RegisterR10 = 10
    X64_RegisterR11 = 11
    X64_RegisterR12 = 12
    X64_RegisterR13 = 13
    X64_RegisterR14 = 14
    X64_RegisterR15 = 15
    X64_RegisterRip = 16
    X64_RegisterRFlags = 17
    X64_RegisterXmm0 = 18
    X64_RegisterXmm1 = 19
    X64_RegisterXmm2 = 20
    X64_RegisterXmm3 = 21
    X64_RegisterXmm4 = 22
    X64_RegisterXmm5 = 23
    X64_RegisterXmm6 = 24
    X64_RegisterXmm7 = 25
    X64_RegisterXmm8 = 26
    X64_RegisterXmm9 = 27
    X64_RegisterXmm10 = 28
    X64_RegisterXmm11 = 29
    X64_RegisterXmm12 = 30
    X64_RegisterXmm13 = 31
    X64_RegisterXmm14 = 32
    X64_RegisterXmm15 = 33
    X64_RegisterFpMmx0 = 34
    X64_RegisterFpMmx1 = 35
    X64_RegisterFpMmx2 = 36
    X64_RegisterFpMmx3 = 37
    X64_RegisterFpMmx4 = 38
    X64_RegisterFpMmx5 = 39
    X64_RegisterFpMmx6 = 40
    X64_RegisterFpMmx7 = 41
    X64_RegisterFpControlStatus = 42
    X64_RegisterXmmControlStatus = 43
    X64_RegisterCr0 = 44
    X64_RegisterCr2 = 45
    X64_RegisterCr3 = 46
    X64_RegisterCr4 = 47
    X64_RegisterCr8 = 48
    X64_RegisterEfer = 49
    X64_RegisterDr0 = 50
    X64_RegisterDr1 = 51
    X64_RegisterDr2 = 52
    X64_RegisterDr3 = 53
    X64_RegisterDr6 = 54
    X64_RegisterDr7 = 55
    X64_RegisterEs = 56
    X64_RegisterCs = 57
    X64_RegisterSs = 58
    X64_RegisterDs = 59
    X64_RegisterFs = 60
    X64_RegisterGs = 61
    X64_RegisterLdtr = 62
    X64_RegisterTr = 63
    X64_RegisterIdtr = 64
    X64_RegisterGdtr = 65
    X64_RegisterMax = 66
    ARM64_RegisterX0 = 67
    ARM64_RegisterX1 = 68
    ARM64_RegisterX2 = 69
    ARM64_RegisterX3 = 70
    ARM64_RegisterX4 = 71
    ARM64_RegisterX5 = 72
    ARM64_RegisterX6 = 73
    ARM64_RegisterX7 = 74
    ARM64_RegisterX8 = 75
    ARM64_RegisterX9 = 76
    ARM64_RegisterX10 = 77
    ARM64_RegisterX11 = 78
    ARM64_RegisterX12 = 79
    ARM64_RegisterX13 = 80
    ARM64_RegisterX14 = 81
    ARM64_RegisterX15 = 82
    ARM64_RegisterX16 = 83
    ARM64_RegisterX17 = 84
    ARM64_RegisterX18 = 85
    ARM64_RegisterX19 = 86
    ARM64_RegisterX20 = 87
    ARM64_RegisterX21 = 88
    ARM64_RegisterX22 = 89
    ARM64_RegisterX23 = 90
    ARM64_RegisterX24 = 91
    ARM64_RegisterX25 = 92
    ARM64_RegisterX26 = 93
    ARM64_RegisterX27 = 94
    ARM64_RegisterX28 = 95
    ARM64_RegisterXFp = 96
    ARM64_RegisterXLr = 97
    ARM64_RegisterPc = 98
    ARM64_RegisterSpEl0 = 99
    ARM64_RegisterSpEl1 = 100
    ARM64_RegisterCpsr = 101
    ARM64_RegisterQ0 = 102
    ARM64_RegisterQ1 = 103
    ARM64_RegisterQ2 = 104
    ARM64_RegisterQ3 = 105
    ARM64_RegisterQ4 = 106
    ARM64_RegisterQ5 = 107
    ARM64_RegisterQ6 = 108
    ARM64_RegisterQ7 = 109
    ARM64_RegisterQ8 = 110
    ARM64_RegisterQ9 = 111
    ARM64_RegisterQ10 = 112
    ARM64_RegisterQ11 = 113
    ARM64_RegisterQ12 = 114
    ARM64_RegisterQ13 = 115
    ARM64_RegisterQ14 = 116
    ARM64_RegisterQ15 = 117
    ARM64_RegisterQ16 = 118
    ARM64_RegisterQ17 = 119
    ARM64_RegisterQ18 = 120
    ARM64_RegisterQ19 = 121
    ARM64_RegisterQ20 = 122
    ARM64_RegisterQ21 = 123
    ARM64_RegisterQ22 = 124
    ARM64_RegisterQ23 = 125
    ARM64_RegisterQ24 = 126
    ARM64_RegisterQ25 = 127
    ARM64_RegisterQ26 = 128
    ARM64_RegisterQ27 = 129
    ARM64_RegisterQ28 = 130
    ARM64_RegisterQ29 = 131
    ARM64_RegisterQ30 = 132
    ARM64_RegisterQ31 = 133
    ARM64_RegisterFpStatus = 134
    ARM64_RegisterFpControl = 135
    ARM64_RegisterEsrEl1 = 136
    ARM64_RegisterSpsrEl1 = 137
    ARM64_RegisterFarEl1 = 138
    ARM64_RegisterParEl1 = 139
    ARM64_RegisterElrEl1 = 140
    ARM64_RegisterTtbr0El1 = 141
    ARM64_RegisterTtbr1El1 = 142
    ARM64_RegisterVbarEl1 = 143
    ARM64_RegisterSctlrEl1 = 144
    ARM64_RegisterActlrEl1 = 145
    ARM64_RegisterTcrEl1 = 146
    ARM64_RegisterMairEl1 = 147
    ARM64_RegisterAmairEl1 = 148
    ARM64_RegisterTpidrEl0 = 149
    ARM64_RegisterTpidrroEl0 = 150
    ARM64_RegisterTpidrEl1 = 151
    ARM64_RegisterContextIdrEl1 = 152
    ARM64_RegisterCpacrEl1 = 153
    ARM64_RegisterCsselrEl1 = 154
    ARM64_RegisterCntkctlEl1 = 155
    ARM64_RegisterCntvCvalEl0 = 156
    ARM64_RegisterCntvCtlEl0 = 157
    ARM64_RegisterMax = 158
End Enum

import enum

class REGISTER_ID(enum.IntEnum):
    X64_RegisterRax = 0
    X64_RegisterRcx = 1
    X64_RegisterRdx = 2
    X64_RegisterRbx = 3
    X64_RegisterRsp = 4
    X64_RegisterRbp = 5
    X64_RegisterRsi = 6
    X64_RegisterRdi = 7
    X64_RegisterR8 = 8
    X64_RegisterR9 = 9
    X64_RegisterR10 = 10
    X64_RegisterR11 = 11
    X64_RegisterR12 = 12
    X64_RegisterR13 = 13
    X64_RegisterR14 = 14
    X64_RegisterR15 = 15
    X64_RegisterRip = 16
    X64_RegisterRFlags = 17
    X64_RegisterXmm0 = 18
    X64_RegisterXmm1 = 19
    X64_RegisterXmm2 = 20
    X64_RegisterXmm3 = 21
    X64_RegisterXmm4 = 22
    X64_RegisterXmm5 = 23
    X64_RegisterXmm6 = 24
    X64_RegisterXmm7 = 25
    X64_RegisterXmm8 = 26
    X64_RegisterXmm9 = 27
    X64_RegisterXmm10 = 28
    X64_RegisterXmm11 = 29
    X64_RegisterXmm12 = 30
    X64_RegisterXmm13 = 31
    X64_RegisterXmm14 = 32
    X64_RegisterXmm15 = 33
    X64_RegisterFpMmx0 = 34
    X64_RegisterFpMmx1 = 35
    X64_RegisterFpMmx2 = 36
    X64_RegisterFpMmx3 = 37
    X64_RegisterFpMmx4 = 38
    X64_RegisterFpMmx5 = 39
    X64_RegisterFpMmx6 = 40
    X64_RegisterFpMmx7 = 41
    X64_RegisterFpControlStatus = 42
    X64_RegisterXmmControlStatus = 43
    X64_RegisterCr0 = 44
    X64_RegisterCr2 = 45
    X64_RegisterCr3 = 46
    X64_RegisterCr4 = 47
    X64_RegisterCr8 = 48
    X64_RegisterEfer = 49
    X64_RegisterDr0 = 50
    X64_RegisterDr1 = 51
    X64_RegisterDr2 = 52
    X64_RegisterDr3 = 53
    X64_RegisterDr6 = 54
    X64_RegisterDr7 = 55
    X64_RegisterEs = 56
    X64_RegisterCs = 57
    X64_RegisterSs = 58
    X64_RegisterDs = 59
    X64_RegisterFs = 60
    X64_RegisterGs = 61
    X64_RegisterLdtr = 62
    X64_RegisterTr = 63
    X64_RegisterIdtr = 64
    X64_RegisterGdtr = 65
    X64_RegisterMax = 66
    ARM64_RegisterX0 = 67
    ARM64_RegisterX1 = 68
    ARM64_RegisterX2 = 69
    ARM64_RegisterX3 = 70
    ARM64_RegisterX4 = 71
    ARM64_RegisterX5 = 72
    ARM64_RegisterX6 = 73
    ARM64_RegisterX7 = 74
    ARM64_RegisterX8 = 75
    ARM64_RegisterX9 = 76
    ARM64_RegisterX10 = 77
    ARM64_RegisterX11 = 78
    ARM64_RegisterX12 = 79
    ARM64_RegisterX13 = 80
    ARM64_RegisterX14 = 81
    ARM64_RegisterX15 = 82
    ARM64_RegisterX16 = 83
    ARM64_RegisterX17 = 84
    ARM64_RegisterX18 = 85
    ARM64_RegisterX19 = 86
    ARM64_RegisterX20 = 87
    ARM64_RegisterX21 = 88
    ARM64_RegisterX22 = 89
    ARM64_RegisterX23 = 90
    ARM64_RegisterX24 = 91
    ARM64_RegisterX25 = 92
    ARM64_RegisterX26 = 93
    ARM64_RegisterX27 = 94
    ARM64_RegisterX28 = 95
    ARM64_RegisterXFp = 96
    ARM64_RegisterXLr = 97
    ARM64_RegisterPc = 98
    ARM64_RegisterSpEl0 = 99
    ARM64_RegisterSpEl1 = 100
    ARM64_RegisterCpsr = 101
    ARM64_RegisterQ0 = 102
    ARM64_RegisterQ1 = 103
    ARM64_RegisterQ2 = 104
    ARM64_RegisterQ3 = 105
    ARM64_RegisterQ4 = 106
    ARM64_RegisterQ5 = 107
    ARM64_RegisterQ6 = 108
    ARM64_RegisterQ7 = 109
    ARM64_RegisterQ8 = 110
    ARM64_RegisterQ9 = 111
    ARM64_RegisterQ10 = 112
    ARM64_RegisterQ11 = 113
    ARM64_RegisterQ12 = 114
    ARM64_RegisterQ13 = 115
    ARM64_RegisterQ14 = 116
    ARM64_RegisterQ15 = 117
    ARM64_RegisterQ16 = 118
    ARM64_RegisterQ17 = 119
    ARM64_RegisterQ18 = 120
    ARM64_RegisterQ19 = 121
    ARM64_RegisterQ20 = 122
    ARM64_RegisterQ21 = 123
    ARM64_RegisterQ22 = 124
    ARM64_RegisterQ23 = 125
    ARM64_RegisterQ24 = 126
    ARM64_RegisterQ25 = 127
    ARM64_RegisterQ26 = 128
    ARM64_RegisterQ27 = 129
    ARM64_RegisterQ28 = 130
    ARM64_RegisterQ29 = 131
    ARM64_RegisterQ30 = 132
    ARM64_RegisterQ31 = 133
    ARM64_RegisterFpStatus = 134
    ARM64_RegisterFpControl = 135
    ARM64_RegisterEsrEl1 = 136
    ARM64_RegisterSpsrEl1 = 137
    ARM64_RegisterFarEl1 = 138
    ARM64_RegisterParEl1 = 139
    ARM64_RegisterElrEl1 = 140
    ARM64_RegisterTtbr0El1 = 141
    ARM64_RegisterTtbr1El1 = 142
    ARM64_RegisterVbarEl1 = 143
    ARM64_RegisterSctlrEl1 = 144
    ARM64_RegisterActlrEl1 = 145
    ARM64_RegisterTcrEl1 = 146
    ARM64_RegisterMairEl1 = 147
    ARM64_RegisterAmairEl1 = 148
    ARM64_RegisterTpidrEl0 = 149
    ARM64_RegisterTpidrroEl0 = 150
    ARM64_RegisterTpidrEl1 = 151
    ARM64_RegisterContextIdrEl1 = 152
    ARM64_RegisterCpacrEl1 = 153
    ARM64_RegisterCsselrEl1 = 154
    ARM64_RegisterCntkctlEl1 = 155
    ARM64_RegisterCntvCvalEl0 = 156
    ARM64_RegisterCntvCtlEl0 = 157
    ARM64_RegisterMax = 158

// REGISTER_ID
pub const X64_RegisterRax: i32 = 0;
pub const X64_RegisterRcx: i32 = 1;
pub const X64_RegisterRdx: i32 = 2;
pub const X64_RegisterRbx: i32 = 3;
pub const X64_RegisterRsp: i32 = 4;
pub const X64_RegisterRbp: i32 = 5;
pub const X64_RegisterRsi: i32 = 6;
pub const X64_RegisterRdi: i32 = 7;
pub const X64_RegisterR8: i32 = 8;
pub const X64_RegisterR9: i32 = 9;
pub const X64_RegisterR10: i32 = 10;
pub const X64_RegisterR11: i32 = 11;
pub const X64_RegisterR12: i32 = 12;
pub const X64_RegisterR13: i32 = 13;
pub const X64_RegisterR14: i32 = 14;
pub const X64_RegisterR15: i32 = 15;
pub const X64_RegisterRip: i32 = 16;
pub const X64_RegisterRFlags: i32 = 17;
pub const X64_RegisterXmm0: i32 = 18;
pub const X64_RegisterXmm1: i32 = 19;
pub const X64_RegisterXmm2: i32 = 20;
pub const X64_RegisterXmm3: i32 = 21;
pub const X64_RegisterXmm4: i32 = 22;
pub const X64_RegisterXmm5: i32 = 23;
pub const X64_RegisterXmm6: i32 = 24;
pub const X64_RegisterXmm7: i32 = 25;
pub const X64_RegisterXmm8: i32 = 26;
pub const X64_RegisterXmm9: i32 = 27;
pub const X64_RegisterXmm10: i32 = 28;
pub const X64_RegisterXmm11: i32 = 29;
pub const X64_RegisterXmm12: i32 = 30;
pub const X64_RegisterXmm13: i32 = 31;
pub const X64_RegisterXmm14: i32 = 32;
pub const X64_RegisterXmm15: i32 = 33;
pub const X64_RegisterFpMmx0: i32 = 34;
pub const X64_RegisterFpMmx1: i32 = 35;
pub const X64_RegisterFpMmx2: i32 = 36;
pub const X64_RegisterFpMmx3: i32 = 37;
pub const X64_RegisterFpMmx4: i32 = 38;
pub const X64_RegisterFpMmx5: i32 = 39;
pub const X64_RegisterFpMmx6: i32 = 40;
pub const X64_RegisterFpMmx7: i32 = 41;
pub const X64_RegisterFpControlStatus: i32 = 42;
pub const X64_RegisterXmmControlStatus: i32 = 43;
pub const X64_RegisterCr0: i32 = 44;
pub const X64_RegisterCr2: i32 = 45;
pub const X64_RegisterCr3: i32 = 46;
pub const X64_RegisterCr4: i32 = 47;
pub const X64_RegisterCr8: i32 = 48;
pub const X64_RegisterEfer: i32 = 49;
pub const X64_RegisterDr0: i32 = 50;
pub const X64_RegisterDr1: i32 = 51;
pub const X64_RegisterDr2: i32 = 52;
pub const X64_RegisterDr3: i32 = 53;
pub const X64_RegisterDr6: i32 = 54;
pub const X64_RegisterDr7: i32 = 55;
pub const X64_RegisterEs: i32 = 56;
pub const X64_RegisterCs: i32 = 57;
pub const X64_RegisterSs: i32 = 58;
pub const X64_RegisterDs: i32 = 59;
pub const X64_RegisterFs: i32 = 60;
pub const X64_RegisterGs: i32 = 61;
pub const X64_RegisterLdtr: i32 = 62;
pub const X64_RegisterTr: i32 = 63;
pub const X64_RegisterIdtr: i32 = 64;
pub const X64_RegisterGdtr: i32 = 65;
pub const X64_RegisterMax: i32 = 66;
pub const ARM64_RegisterX0: i32 = 67;
pub const ARM64_RegisterX1: i32 = 68;
pub const ARM64_RegisterX2: i32 = 69;
pub const ARM64_RegisterX3: i32 = 70;
pub const ARM64_RegisterX4: i32 = 71;
pub const ARM64_RegisterX5: i32 = 72;
pub const ARM64_RegisterX6: i32 = 73;
pub const ARM64_RegisterX7: i32 = 74;
pub const ARM64_RegisterX8: i32 = 75;
pub const ARM64_RegisterX9: i32 = 76;
pub const ARM64_RegisterX10: i32 = 77;
pub const ARM64_RegisterX11: i32 = 78;
pub const ARM64_RegisterX12: i32 = 79;
pub const ARM64_RegisterX13: i32 = 80;
pub const ARM64_RegisterX14: i32 = 81;
pub const ARM64_RegisterX15: i32 = 82;
pub const ARM64_RegisterX16: i32 = 83;
pub const ARM64_RegisterX17: i32 = 84;
pub const ARM64_RegisterX18: i32 = 85;
pub const ARM64_RegisterX19: i32 = 86;
pub const ARM64_RegisterX20: i32 = 87;
pub const ARM64_RegisterX21: i32 = 88;
pub const ARM64_RegisterX22: i32 = 89;
pub const ARM64_RegisterX23: i32 = 90;
pub const ARM64_RegisterX24: i32 = 91;
pub const ARM64_RegisterX25: i32 = 92;
pub const ARM64_RegisterX26: i32 = 93;
pub const ARM64_RegisterX27: i32 = 94;
pub const ARM64_RegisterX28: i32 = 95;
pub const ARM64_RegisterXFp: i32 = 96;
pub const ARM64_RegisterXLr: i32 = 97;
pub const ARM64_RegisterPc: i32 = 98;
pub const ARM64_RegisterSpEl0: i32 = 99;
pub const ARM64_RegisterSpEl1: i32 = 100;
pub const ARM64_RegisterCpsr: i32 = 101;
pub const ARM64_RegisterQ0: i32 = 102;
pub const ARM64_RegisterQ1: i32 = 103;
pub const ARM64_RegisterQ2: i32 = 104;
pub const ARM64_RegisterQ3: i32 = 105;
pub const ARM64_RegisterQ4: i32 = 106;
pub const ARM64_RegisterQ5: i32 = 107;
pub const ARM64_RegisterQ6: i32 = 108;
pub const ARM64_RegisterQ7: i32 = 109;
pub const ARM64_RegisterQ8: i32 = 110;
pub const ARM64_RegisterQ9: i32 = 111;
pub const ARM64_RegisterQ10: i32 = 112;
pub const ARM64_RegisterQ11: i32 = 113;
pub const ARM64_RegisterQ12: i32 = 114;
pub const ARM64_RegisterQ13: i32 = 115;
pub const ARM64_RegisterQ14: i32 = 116;
pub const ARM64_RegisterQ15: i32 = 117;
pub const ARM64_RegisterQ16: i32 = 118;
pub const ARM64_RegisterQ17: i32 = 119;
pub const ARM64_RegisterQ18: i32 = 120;
pub const ARM64_RegisterQ19: i32 = 121;
pub const ARM64_RegisterQ20: i32 = 122;
pub const ARM64_RegisterQ21: i32 = 123;
pub const ARM64_RegisterQ22: i32 = 124;
pub const ARM64_RegisterQ23: i32 = 125;
pub const ARM64_RegisterQ24: i32 = 126;
pub const ARM64_RegisterQ25: i32 = 127;
pub const ARM64_RegisterQ26: i32 = 128;
pub const ARM64_RegisterQ27: i32 = 129;
pub const ARM64_RegisterQ28: i32 = 130;
pub const ARM64_RegisterQ29: i32 = 131;
pub const ARM64_RegisterQ30: i32 = 132;
pub const ARM64_RegisterQ31: i32 = 133;
pub const ARM64_RegisterFpStatus: i32 = 134;
pub const ARM64_RegisterFpControl: i32 = 135;
pub const ARM64_RegisterEsrEl1: i32 = 136;
pub const ARM64_RegisterSpsrEl1: i32 = 137;
pub const ARM64_RegisterFarEl1: i32 = 138;
pub const ARM64_RegisterParEl1: i32 = 139;
pub const ARM64_RegisterElrEl1: i32 = 140;
pub const ARM64_RegisterTtbr0El1: i32 = 141;
pub const ARM64_RegisterTtbr1El1: i32 = 142;
pub const ARM64_RegisterVbarEl1: i32 = 143;
pub const ARM64_RegisterSctlrEl1: i32 = 144;
pub const ARM64_RegisterActlrEl1: i32 = 145;
pub const ARM64_RegisterTcrEl1: i32 = 146;
pub const ARM64_RegisterMairEl1: i32 = 147;
pub const ARM64_RegisterAmairEl1: i32 = 148;
pub const ARM64_RegisterTpidrEl0: i32 = 149;
pub const ARM64_RegisterTpidrroEl0: i32 = 150;
pub const ARM64_RegisterTpidrEl1: i32 = 151;
pub const ARM64_RegisterContextIdrEl1: i32 = 152;
pub const ARM64_RegisterCpacrEl1: i32 = 153;
pub const ARM64_RegisterCsselrEl1: i32 = 154;
pub const ARM64_RegisterCntkctlEl1: i32 = 155;
pub const ARM64_RegisterCntvCvalEl0: i32 = 156;
pub const ARM64_RegisterCntvCtlEl0: i32 = 157;
pub const ARM64_RegisterMax: i32 = 158;

// REGISTER_ID
const (
	X64_RegisterRax int32 = 0
	X64_RegisterRcx int32 = 1
	X64_RegisterRdx int32 = 2
	X64_RegisterRbx int32 = 3
	X64_RegisterRsp int32 = 4
	X64_RegisterRbp int32 = 5
	X64_RegisterRsi int32 = 6
	X64_RegisterRdi int32 = 7
	X64_RegisterR8 int32 = 8
	X64_RegisterR9 int32 = 9
	X64_RegisterR10 int32 = 10
	X64_RegisterR11 int32 = 11
	X64_RegisterR12 int32 = 12
	X64_RegisterR13 int32 = 13
	X64_RegisterR14 int32 = 14
	X64_RegisterR15 int32 = 15
	X64_RegisterRip int32 = 16
	X64_RegisterRFlags int32 = 17
	X64_RegisterXmm0 int32 = 18
	X64_RegisterXmm1 int32 = 19
	X64_RegisterXmm2 int32 = 20
	X64_RegisterXmm3 int32 = 21
	X64_RegisterXmm4 int32 = 22
	X64_RegisterXmm5 int32 = 23
	X64_RegisterXmm6 int32 = 24
	X64_RegisterXmm7 int32 = 25
	X64_RegisterXmm8 int32 = 26
	X64_RegisterXmm9 int32 = 27
	X64_RegisterXmm10 int32 = 28
	X64_RegisterXmm11 int32 = 29
	X64_RegisterXmm12 int32 = 30
	X64_RegisterXmm13 int32 = 31
	X64_RegisterXmm14 int32 = 32
	X64_RegisterXmm15 int32 = 33
	X64_RegisterFpMmx0 int32 = 34
	X64_RegisterFpMmx1 int32 = 35
	X64_RegisterFpMmx2 int32 = 36
	X64_RegisterFpMmx3 int32 = 37
	X64_RegisterFpMmx4 int32 = 38
	X64_RegisterFpMmx5 int32 = 39
	X64_RegisterFpMmx6 int32 = 40
	X64_RegisterFpMmx7 int32 = 41
	X64_RegisterFpControlStatus int32 = 42
	X64_RegisterXmmControlStatus int32 = 43
	X64_RegisterCr0 int32 = 44
	X64_RegisterCr2 int32 = 45
	X64_RegisterCr3 int32 = 46
	X64_RegisterCr4 int32 = 47
	X64_RegisterCr8 int32 = 48
	X64_RegisterEfer int32 = 49
	X64_RegisterDr0 int32 = 50
	X64_RegisterDr1 int32 = 51
	X64_RegisterDr2 int32 = 52
	X64_RegisterDr3 int32 = 53
	X64_RegisterDr6 int32 = 54
	X64_RegisterDr7 int32 = 55
	X64_RegisterEs int32 = 56
	X64_RegisterCs int32 = 57
	X64_RegisterSs int32 = 58
	X64_RegisterDs int32 = 59
	X64_RegisterFs int32 = 60
	X64_RegisterGs int32 = 61
	X64_RegisterLdtr int32 = 62
	X64_RegisterTr int32 = 63
	X64_RegisterIdtr int32 = 64
	X64_RegisterGdtr int32 = 65
	X64_RegisterMax int32 = 66
	ARM64_RegisterX0 int32 = 67
	ARM64_RegisterX1 int32 = 68
	ARM64_RegisterX2 int32 = 69
	ARM64_RegisterX3 int32 = 70
	ARM64_RegisterX4 int32 = 71
	ARM64_RegisterX5 int32 = 72
	ARM64_RegisterX6 int32 = 73
	ARM64_RegisterX7 int32 = 74
	ARM64_RegisterX8 int32 = 75
	ARM64_RegisterX9 int32 = 76
	ARM64_RegisterX10 int32 = 77
	ARM64_RegisterX11 int32 = 78
	ARM64_RegisterX12 int32 = 79
	ARM64_RegisterX13 int32 = 80
	ARM64_RegisterX14 int32 = 81
	ARM64_RegisterX15 int32 = 82
	ARM64_RegisterX16 int32 = 83
	ARM64_RegisterX17 int32 = 84
	ARM64_RegisterX18 int32 = 85
	ARM64_RegisterX19 int32 = 86
	ARM64_RegisterX20 int32 = 87
	ARM64_RegisterX21 int32 = 88
	ARM64_RegisterX22 int32 = 89
	ARM64_RegisterX23 int32 = 90
	ARM64_RegisterX24 int32 = 91
	ARM64_RegisterX25 int32 = 92
	ARM64_RegisterX26 int32 = 93
	ARM64_RegisterX27 int32 = 94
	ARM64_RegisterX28 int32 = 95
	ARM64_RegisterXFp int32 = 96
	ARM64_RegisterXLr int32 = 97
	ARM64_RegisterPc int32 = 98
	ARM64_RegisterSpEl0 int32 = 99
	ARM64_RegisterSpEl1 int32 = 100
	ARM64_RegisterCpsr int32 = 101
	ARM64_RegisterQ0 int32 = 102
	ARM64_RegisterQ1 int32 = 103
	ARM64_RegisterQ2 int32 = 104
	ARM64_RegisterQ3 int32 = 105
	ARM64_RegisterQ4 int32 = 106
	ARM64_RegisterQ5 int32 = 107
	ARM64_RegisterQ6 int32 = 108
	ARM64_RegisterQ7 int32 = 109
	ARM64_RegisterQ8 int32 = 110
	ARM64_RegisterQ9 int32 = 111
	ARM64_RegisterQ10 int32 = 112
	ARM64_RegisterQ11 int32 = 113
	ARM64_RegisterQ12 int32 = 114
	ARM64_RegisterQ13 int32 = 115
	ARM64_RegisterQ14 int32 = 116
	ARM64_RegisterQ15 int32 = 117
	ARM64_RegisterQ16 int32 = 118
	ARM64_RegisterQ17 int32 = 119
	ARM64_RegisterQ18 int32 = 120
	ARM64_RegisterQ19 int32 = 121
	ARM64_RegisterQ20 int32 = 122
	ARM64_RegisterQ21 int32 = 123
	ARM64_RegisterQ22 int32 = 124
	ARM64_RegisterQ23 int32 = 125
	ARM64_RegisterQ24 int32 = 126
	ARM64_RegisterQ25 int32 = 127
	ARM64_RegisterQ26 int32 = 128
	ARM64_RegisterQ27 int32 = 129
	ARM64_RegisterQ28 int32 = 130
	ARM64_RegisterQ29 int32 = 131
	ARM64_RegisterQ30 int32 = 132
	ARM64_RegisterQ31 int32 = 133
	ARM64_RegisterFpStatus int32 = 134
	ARM64_RegisterFpControl int32 = 135
	ARM64_RegisterEsrEl1 int32 = 136
	ARM64_RegisterSpsrEl1 int32 = 137
	ARM64_RegisterFarEl1 int32 = 138
	ARM64_RegisterParEl1 int32 = 139
	ARM64_RegisterElrEl1 int32 = 140
	ARM64_RegisterTtbr0El1 int32 = 141
	ARM64_RegisterTtbr1El1 int32 = 142
	ARM64_RegisterVbarEl1 int32 = 143
	ARM64_RegisterSctlrEl1 int32 = 144
	ARM64_RegisterActlrEl1 int32 = 145
	ARM64_RegisterTcrEl1 int32 = 146
	ARM64_RegisterMairEl1 int32 = 147
	ARM64_RegisterAmairEl1 int32 = 148
	ARM64_RegisterTpidrEl0 int32 = 149
	ARM64_RegisterTpidrroEl0 int32 = 150
	ARM64_RegisterTpidrEl1 int32 = 151
	ARM64_RegisterContextIdrEl1 int32 = 152
	ARM64_RegisterCpacrEl1 int32 = 153
	ARM64_RegisterCsselrEl1 int32 = 154
	ARM64_RegisterCntkctlEl1 int32 = 155
	ARM64_RegisterCntvCvalEl0 int32 = 156
	ARM64_RegisterCntvCtlEl0 int32 = 157
	ARM64_RegisterMax int32 = 158
)

const
  X64_RegisterRax = 0;
  X64_RegisterRcx = 1;
  X64_RegisterRdx = 2;
  X64_RegisterRbx = 3;
  X64_RegisterRsp = 4;
  X64_RegisterRbp = 5;
  X64_RegisterRsi = 6;
  X64_RegisterRdi = 7;
  X64_RegisterR8 = 8;
  X64_RegisterR9 = 9;
  X64_RegisterR10 = 10;
  X64_RegisterR11 = 11;
  X64_RegisterR12 = 12;
  X64_RegisterR13 = 13;
  X64_RegisterR14 = 14;
  X64_RegisterR15 = 15;
  X64_RegisterRip = 16;
  X64_RegisterRFlags = 17;
  X64_RegisterXmm0 = 18;
  X64_RegisterXmm1 = 19;
  X64_RegisterXmm2 = 20;
  X64_RegisterXmm3 = 21;
  X64_RegisterXmm4 = 22;
  X64_RegisterXmm5 = 23;
  X64_RegisterXmm6 = 24;
  X64_RegisterXmm7 = 25;
  X64_RegisterXmm8 = 26;
  X64_RegisterXmm9 = 27;
  X64_RegisterXmm10 = 28;
  X64_RegisterXmm11 = 29;
  X64_RegisterXmm12 = 30;
  X64_RegisterXmm13 = 31;
  X64_RegisterXmm14 = 32;
  X64_RegisterXmm15 = 33;
  X64_RegisterFpMmx0 = 34;
  X64_RegisterFpMmx1 = 35;
  X64_RegisterFpMmx2 = 36;
  X64_RegisterFpMmx3 = 37;
  X64_RegisterFpMmx4 = 38;
  X64_RegisterFpMmx5 = 39;
  X64_RegisterFpMmx6 = 40;
  X64_RegisterFpMmx7 = 41;
  X64_RegisterFpControlStatus = 42;
  X64_RegisterXmmControlStatus = 43;
  X64_RegisterCr0 = 44;
  X64_RegisterCr2 = 45;
  X64_RegisterCr3 = 46;
  X64_RegisterCr4 = 47;
  X64_RegisterCr8 = 48;
  X64_RegisterEfer = 49;
  X64_RegisterDr0 = 50;
  X64_RegisterDr1 = 51;
  X64_RegisterDr2 = 52;
  X64_RegisterDr3 = 53;
  X64_RegisterDr6 = 54;
  X64_RegisterDr7 = 55;
  X64_RegisterEs = 56;
  X64_RegisterCs = 57;
  X64_RegisterSs = 58;
  X64_RegisterDs = 59;
  X64_RegisterFs = 60;
  X64_RegisterGs = 61;
  X64_RegisterLdtr = 62;
  X64_RegisterTr = 63;
  X64_RegisterIdtr = 64;
  X64_RegisterGdtr = 65;
  X64_RegisterMax = 66;
  ARM64_RegisterX0 = 67;
  ARM64_RegisterX1 = 68;
  ARM64_RegisterX2 = 69;
  ARM64_RegisterX3 = 70;
  ARM64_RegisterX4 = 71;
  ARM64_RegisterX5 = 72;
  ARM64_RegisterX6 = 73;
  ARM64_RegisterX7 = 74;
  ARM64_RegisterX8 = 75;
  ARM64_RegisterX9 = 76;
  ARM64_RegisterX10 = 77;
  ARM64_RegisterX11 = 78;
  ARM64_RegisterX12 = 79;
  ARM64_RegisterX13 = 80;
  ARM64_RegisterX14 = 81;
  ARM64_RegisterX15 = 82;
  ARM64_RegisterX16 = 83;
  ARM64_RegisterX17 = 84;
  ARM64_RegisterX18 = 85;
  ARM64_RegisterX19 = 86;
  ARM64_RegisterX20 = 87;
  ARM64_RegisterX21 = 88;
  ARM64_RegisterX22 = 89;
  ARM64_RegisterX23 = 90;
  ARM64_RegisterX24 = 91;
  ARM64_RegisterX25 = 92;
  ARM64_RegisterX26 = 93;
  ARM64_RegisterX27 = 94;
  ARM64_RegisterX28 = 95;
  ARM64_RegisterXFp = 96;
  ARM64_RegisterXLr = 97;
  ARM64_RegisterPc = 98;
  ARM64_RegisterSpEl0 = 99;
  ARM64_RegisterSpEl1 = 100;
  ARM64_RegisterCpsr = 101;
  ARM64_RegisterQ0 = 102;
  ARM64_RegisterQ1 = 103;
  ARM64_RegisterQ2 = 104;
  ARM64_RegisterQ3 = 105;
  ARM64_RegisterQ4 = 106;
  ARM64_RegisterQ5 = 107;
  ARM64_RegisterQ6 = 108;
  ARM64_RegisterQ7 = 109;
  ARM64_RegisterQ8 = 110;
  ARM64_RegisterQ9 = 111;
  ARM64_RegisterQ10 = 112;
  ARM64_RegisterQ11 = 113;
  ARM64_RegisterQ12 = 114;
  ARM64_RegisterQ13 = 115;
  ARM64_RegisterQ14 = 116;
  ARM64_RegisterQ15 = 117;
  ARM64_RegisterQ16 = 118;
  ARM64_RegisterQ17 = 119;
  ARM64_RegisterQ18 = 120;
  ARM64_RegisterQ19 = 121;
  ARM64_RegisterQ20 = 122;
  ARM64_RegisterQ21 = 123;
  ARM64_RegisterQ22 = 124;
  ARM64_RegisterQ23 = 125;
  ARM64_RegisterQ24 = 126;
  ARM64_RegisterQ25 = 127;
  ARM64_RegisterQ26 = 128;
  ARM64_RegisterQ27 = 129;
  ARM64_RegisterQ28 = 130;
  ARM64_RegisterQ29 = 131;
  ARM64_RegisterQ30 = 132;
  ARM64_RegisterQ31 = 133;
  ARM64_RegisterFpStatus = 134;
  ARM64_RegisterFpControl = 135;
  ARM64_RegisterEsrEl1 = 136;
  ARM64_RegisterSpsrEl1 = 137;
  ARM64_RegisterFarEl1 = 138;
  ARM64_RegisterParEl1 = 139;
  ARM64_RegisterElrEl1 = 140;
  ARM64_RegisterTtbr0El1 = 141;
  ARM64_RegisterTtbr1El1 = 142;
  ARM64_RegisterVbarEl1 = 143;
  ARM64_RegisterSctlrEl1 = 144;
  ARM64_RegisterActlrEl1 = 145;
  ARM64_RegisterTcrEl1 = 146;
  ARM64_RegisterMairEl1 = 147;
  ARM64_RegisterAmairEl1 = 148;
  ARM64_RegisterTpidrEl0 = 149;
  ARM64_RegisterTpidrroEl0 = 150;
  ARM64_RegisterTpidrEl1 = 151;
  ARM64_RegisterContextIdrEl1 = 152;
  ARM64_RegisterCpacrEl1 = 153;
  ARM64_RegisterCsselrEl1 = 154;
  ARM64_RegisterCntkctlEl1 = 155;
  ARM64_RegisterCntvCvalEl0 = 156;
  ARM64_RegisterCntvCtlEl0 = 157;
  ARM64_RegisterMax = 158;

// REGISTER_ID
pub const X64_RegisterRax: i32 = 0;
pub const X64_RegisterRcx: i32 = 1;
pub const X64_RegisterRdx: i32 = 2;
pub const X64_RegisterRbx: i32 = 3;
pub const X64_RegisterRsp: i32 = 4;
pub const X64_RegisterRbp: i32 = 5;
pub const X64_RegisterRsi: i32 = 6;
pub const X64_RegisterRdi: i32 = 7;
pub const X64_RegisterR8: i32 = 8;
pub const X64_RegisterR9: i32 = 9;
pub const X64_RegisterR10: i32 = 10;
pub const X64_RegisterR11: i32 = 11;
pub const X64_RegisterR12: i32 = 12;
pub const X64_RegisterR13: i32 = 13;
pub const X64_RegisterR14: i32 = 14;
pub const X64_RegisterR15: i32 = 15;
pub const X64_RegisterRip: i32 = 16;
pub const X64_RegisterRFlags: i32 = 17;
pub const X64_RegisterXmm0: i32 = 18;
pub const X64_RegisterXmm1: i32 = 19;
pub const X64_RegisterXmm2: i32 = 20;
pub const X64_RegisterXmm3: i32 = 21;
pub const X64_RegisterXmm4: i32 = 22;
pub const X64_RegisterXmm5: i32 = 23;
pub const X64_RegisterXmm6: i32 = 24;
pub const X64_RegisterXmm7: i32 = 25;
pub const X64_RegisterXmm8: i32 = 26;
pub const X64_RegisterXmm9: i32 = 27;
pub const X64_RegisterXmm10: i32 = 28;
pub const X64_RegisterXmm11: i32 = 29;
pub const X64_RegisterXmm12: i32 = 30;
pub const X64_RegisterXmm13: i32 = 31;
pub const X64_RegisterXmm14: i32 = 32;
pub const X64_RegisterXmm15: i32 = 33;
pub const X64_RegisterFpMmx0: i32 = 34;
pub const X64_RegisterFpMmx1: i32 = 35;
pub const X64_RegisterFpMmx2: i32 = 36;
pub const X64_RegisterFpMmx3: i32 = 37;
pub const X64_RegisterFpMmx4: i32 = 38;
pub const X64_RegisterFpMmx5: i32 = 39;
pub const X64_RegisterFpMmx6: i32 = 40;
pub const X64_RegisterFpMmx7: i32 = 41;
pub const X64_RegisterFpControlStatus: i32 = 42;
pub const X64_RegisterXmmControlStatus: i32 = 43;
pub const X64_RegisterCr0: i32 = 44;
pub const X64_RegisterCr2: i32 = 45;
pub const X64_RegisterCr3: i32 = 46;
pub const X64_RegisterCr4: i32 = 47;
pub const X64_RegisterCr8: i32 = 48;
pub const X64_RegisterEfer: i32 = 49;
pub const X64_RegisterDr0: i32 = 50;
pub const X64_RegisterDr1: i32 = 51;
pub const X64_RegisterDr2: i32 = 52;
pub const X64_RegisterDr3: i32 = 53;
pub const X64_RegisterDr6: i32 = 54;
pub const X64_RegisterDr7: i32 = 55;
pub const X64_RegisterEs: i32 = 56;
pub const X64_RegisterCs: i32 = 57;
pub const X64_RegisterSs: i32 = 58;
pub const X64_RegisterDs: i32 = 59;
pub const X64_RegisterFs: i32 = 60;
pub const X64_RegisterGs: i32 = 61;
pub const X64_RegisterLdtr: i32 = 62;
pub const X64_RegisterTr: i32 = 63;
pub const X64_RegisterIdtr: i32 = 64;
pub const X64_RegisterGdtr: i32 = 65;
pub const X64_RegisterMax: i32 = 66;
pub const ARM64_RegisterX0: i32 = 67;
pub const ARM64_RegisterX1: i32 = 68;
pub const ARM64_RegisterX2: i32 = 69;
pub const ARM64_RegisterX3: i32 = 70;
pub const ARM64_RegisterX4: i32 = 71;
pub const ARM64_RegisterX5: i32 = 72;
pub const ARM64_RegisterX6: i32 = 73;
pub const ARM64_RegisterX7: i32 = 74;
pub const ARM64_RegisterX8: i32 = 75;
pub const ARM64_RegisterX9: i32 = 76;
pub const ARM64_RegisterX10: i32 = 77;
pub const ARM64_RegisterX11: i32 = 78;
pub const ARM64_RegisterX12: i32 = 79;
pub const ARM64_RegisterX13: i32 = 80;
pub const ARM64_RegisterX14: i32 = 81;
pub const ARM64_RegisterX15: i32 = 82;
pub const ARM64_RegisterX16: i32 = 83;
pub const ARM64_RegisterX17: i32 = 84;
pub const ARM64_RegisterX18: i32 = 85;
pub const ARM64_RegisterX19: i32 = 86;
pub const ARM64_RegisterX20: i32 = 87;
pub const ARM64_RegisterX21: i32 = 88;
pub const ARM64_RegisterX22: i32 = 89;
pub const ARM64_RegisterX23: i32 = 90;
pub const ARM64_RegisterX24: i32 = 91;
pub const ARM64_RegisterX25: i32 = 92;
pub const ARM64_RegisterX26: i32 = 93;
pub const ARM64_RegisterX27: i32 = 94;
pub const ARM64_RegisterX28: i32 = 95;
pub const ARM64_RegisterXFp: i32 = 96;
pub const ARM64_RegisterXLr: i32 = 97;
pub const ARM64_RegisterPc: i32 = 98;
pub const ARM64_RegisterSpEl0: i32 = 99;
pub const ARM64_RegisterSpEl1: i32 = 100;
pub const ARM64_RegisterCpsr: i32 = 101;
pub const ARM64_RegisterQ0: i32 = 102;
pub const ARM64_RegisterQ1: i32 = 103;
pub const ARM64_RegisterQ2: i32 = 104;
pub const ARM64_RegisterQ3: i32 = 105;
pub const ARM64_RegisterQ4: i32 = 106;
pub const ARM64_RegisterQ5: i32 = 107;
pub const ARM64_RegisterQ6: i32 = 108;
pub const ARM64_RegisterQ7: i32 = 109;
pub const ARM64_RegisterQ8: i32 = 110;
pub const ARM64_RegisterQ9: i32 = 111;
pub const ARM64_RegisterQ10: i32 = 112;
pub const ARM64_RegisterQ11: i32 = 113;
pub const ARM64_RegisterQ12: i32 = 114;
pub const ARM64_RegisterQ13: i32 = 115;
pub const ARM64_RegisterQ14: i32 = 116;
pub const ARM64_RegisterQ15: i32 = 117;
pub const ARM64_RegisterQ16: i32 = 118;
pub const ARM64_RegisterQ17: i32 = 119;
pub const ARM64_RegisterQ18: i32 = 120;
pub const ARM64_RegisterQ19: i32 = 121;
pub const ARM64_RegisterQ20: i32 = 122;
pub const ARM64_RegisterQ21: i32 = 123;
pub const ARM64_RegisterQ22: i32 = 124;
pub const ARM64_RegisterQ23: i32 = 125;
pub const ARM64_RegisterQ24: i32 = 126;
pub const ARM64_RegisterQ25: i32 = 127;
pub const ARM64_RegisterQ26: i32 = 128;
pub const ARM64_RegisterQ27: i32 = 129;
pub const ARM64_RegisterQ28: i32 = 130;
pub const ARM64_RegisterQ29: i32 = 131;
pub const ARM64_RegisterQ30: i32 = 132;
pub const ARM64_RegisterQ31: i32 = 133;
pub const ARM64_RegisterFpStatus: i32 = 134;
pub const ARM64_RegisterFpControl: i32 = 135;
pub const ARM64_RegisterEsrEl1: i32 = 136;
pub const ARM64_RegisterSpsrEl1: i32 = 137;
pub const ARM64_RegisterFarEl1: i32 = 138;
pub const ARM64_RegisterParEl1: i32 = 139;
pub const ARM64_RegisterElrEl1: i32 = 140;
pub const ARM64_RegisterTtbr0El1: i32 = 141;
pub const ARM64_RegisterTtbr1El1: i32 = 142;
pub const ARM64_RegisterVbarEl1: i32 = 143;
pub const ARM64_RegisterSctlrEl1: i32 = 144;
pub const ARM64_RegisterActlrEl1: i32 = 145;
pub const ARM64_RegisterTcrEl1: i32 = 146;
pub const ARM64_RegisterMairEl1: i32 = 147;
pub const ARM64_RegisterAmairEl1: i32 = 148;
pub const ARM64_RegisterTpidrEl0: i32 = 149;
pub const ARM64_RegisterTpidrroEl0: i32 = 150;
pub const ARM64_RegisterTpidrEl1: i32 = 151;
pub const ARM64_RegisterContextIdrEl1: i32 = 152;
pub const ARM64_RegisterCpacrEl1: i32 = 153;
pub const ARM64_RegisterCsselrEl1: i32 = 154;
pub const ARM64_RegisterCntkctlEl1: i32 = 155;
pub const ARM64_RegisterCntvCvalEl0: i32 = 156;
pub const ARM64_RegisterCntvCtlEl0: i32 = 157;
pub const ARM64_RegisterMax: i32 = 158;

const
  X64_RegisterRax* = 0
  X64_RegisterRcx* = 1
  X64_RegisterRdx* = 2
  X64_RegisterRbx* = 3
  X64_RegisterRsp* = 4
  X64_RegisterRbp* = 5
  X64_RegisterRsi* = 6
  X64_RegisterRdi* = 7
  X64_RegisterR8* = 8
  X64_RegisterR9* = 9
  X64_RegisterR10* = 10
  X64_RegisterR11* = 11
  X64_RegisterR12* = 12
  X64_RegisterR13* = 13
  X64_RegisterR14* = 14
  X64_RegisterR15* = 15
  X64_RegisterRip* = 16
  X64_RegisterRFlags* = 17
  X64_RegisterXmm0* = 18
  X64_RegisterXmm1* = 19
  X64_RegisterXmm2* = 20
  X64_RegisterXmm3* = 21
  X64_RegisterXmm4* = 22
  X64_RegisterXmm5* = 23
  X64_RegisterXmm6* = 24
  X64_RegisterXmm7* = 25
  X64_RegisterXmm8* = 26
  X64_RegisterXmm9* = 27
  X64_RegisterXmm10* = 28
  X64_RegisterXmm11* = 29
  X64_RegisterXmm12* = 30
  X64_RegisterXmm13* = 31
  X64_RegisterXmm14* = 32
  X64_RegisterXmm15* = 33
  X64_RegisterFpMmx0* = 34
  X64_RegisterFpMmx1* = 35
  X64_RegisterFpMmx2* = 36
  X64_RegisterFpMmx3* = 37
  X64_RegisterFpMmx4* = 38
  X64_RegisterFpMmx5* = 39
  X64_RegisterFpMmx6* = 40
  X64_RegisterFpMmx7* = 41
  X64_RegisterFpControlStatus* = 42
  X64_RegisterXmmControlStatus* = 43
  X64_RegisterCr0* = 44
  X64_RegisterCr2* = 45
  X64_RegisterCr3* = 46
  X64_RegisterCr4* = 47
  X64_RegisterCr8* = 48
  X64_RegisterEfer* = 49
  X64_RegisterDr0* = 50
  X64_RegisterDr1* = 51
  X64_RegisterDr2* = 52
  X64_RegisterDr3* = 53
  X64_RegisterDr6* = 54
  X64_RegisterDr7* = 55
  X64_RegisterEs* = 56
  X64_RegisterCs* = 57
  X64_RegisterSs* = 58
  X64_RegisterDs* = 59
  X64_RegisterFs* = 60
  X64_RegisterGs* = 61
  X64_RegisterLdtr* = 62
  X64_RegisterTr* = 63
  X64_RegisterIdtr* = 64
  X64_RegisterGdtr* = 65
  X64_RegisterMax* = 66
  ARM64_RegisterX0* = 67
  ARM64_RegisterX1* = 68
  ARM64_RegisterX2* = 69
  ARM64_RegisterX3* = 70
  ARM64_RegisterX4* = 71
  ARM64_RegisterX5* = 72
  ARM64_RegisterX6* = 73
  ARM64_RegisterX7* = 74
  ARM64_RegisterX8* = 75
  ARM64_RegisterX9* = 76
  ARM64_RegisterX10* = 77
  ARM64_RegisterX11* = 78
  ARM64_RegisterX12* = 79
  ARM64_RegisterX13* = 80
  ARM64_RegisterX14* = 81
  ARM64_RegisterX15* = 82
  ARM64_RegisterX16* = 83
  ARM64_RegisterX17* = 84
  ARM64_RegisterX18* = 85
  ARM64_RegisterX19* = 86
  ARM64_RegisterX20* = 87
  ARM64_RegisterX21* = 88
  ARM64_RegisterX22* = 89
  ARM64_RegisterX23* = 90
  ARM64_RegisterX24* = 91
  ARM64_RegisterX25* = 92
  ARM64_RegisterX26* = 93
  ARM64_RegisterX27* = 94
  ARM64_RegisterX28* = 95
  ARM64_RegisterXFp* = 96
  ARM64_RegisterXLr* = 97
  ARM64_RegisterPc* = 98
  ARM64_RegisterSpEl0* = 99
  ARM64_RegisterSpEl1* = 100
  ARM64_RegisterCpsr* = 101
  ARM64_RegisterQ0* = 102
  ARM64_RegisterQ1* = 103
  ARM64_RegisterQ2* = 104
  ARM64_RegisterQ3* = 105
  ARM64_RegisterQ4* = 106
  ARM64_RegisterQ5* = 107
  ARM64_RegisterQ6* = 108
  ARM64_RegisterQ7* = 109
  ARM64_RegisterQ8* = 110
  ARM64_RegisterQ9* = 111
  ARM64_RegisterQ10* = 112
  ARM64_RegisterQ11* = 113
  ARM64_RegisterQ12* = 114
  ARM64_RegisterQ13* = 115
  ARM64_RegisterQ14* = 116
  ARM64_RegisterQ15* = 117
  ARM64_RegisterQ16* = 118
  ARM64_RegisterQ17* = 119
  ARM64_RegisterQ18* = 120
  ARM64_RegisterQ19* = 121
  ARM64_RegisterQ20* = 122
  ARM64_RegisterQ21* = 123
  ARM64_RegisterQ22* = 124
  ARM64_RegisterQ23* = 125
  ARM64_RegisterQ24* = 126
  ARM64_RegisterQ25* = 127
  ARM64_RegisterQ26* = 128
  ARM64_RegisterQ27* = 129
  ARM64_RegisterQ28* = 130
  ARM64_RegisterQ29* = 131
  ARM64_RegisterQ30* = 132
  ARM64_RegisterQ31* = 133
  ARM64_RegisterFpStatus* = 134
  ARM64_RegisterFpControl* = 135
  ARM64_RegisterEsrEl1* = 136
  ARM64_RegisterSpsrEl1* = 137
  ARM64_RegisterFarEl1* = 138
  ARM64_RegisterParEl1* = 139
  ARM64_RegisterElrEl1* = 140
  ARM64_RegisterTtbr0El1* = 141
  ARM64_RegisterTtbr1El1* = 142
  ARM64_RegisterVbarEl1* = 143
  ARM64_RegisterSctlrEl1* = 144
  ARM64_RegisterActlrEl1* = 145
  ARM64_RegisterTcrEl1* = 146
  ARM64_RegisterMairEl1* = 147
  ARM64_RegisterAmairEl1* = 148
  ARM64_RegisterTpidrEl0* = 149
  ARM64_RegisterTpidrroEl0* = 150
  ARM64_RegisterTpidrEl1* = 151
  ARM64_RegisterContextIdrEl1* = 152
  ARM64_RegisterCpacrEl1* = 153
  ARM64_RegisterCsselrEl1* = 154
  ARM64_RegisterCntkctlEl1* = 155
  ARM64_RegisterCntvCvalEl0* = 156
  ARM64_RegisterCntvCtlEl0* = 157
  ARM64_RegisterMax* = 158

enum REGISTER_ID : int {
    X64_RegisterRax = 0,
    X64_RegisterRcx = 1,
    X64_RegisterRdx = 2,
    X64_RegisterRbx = 3,
    X64_RegisterRsp = 4,
    X64_RegisterRbp = 5,
    X64_RegisterRsi = 6,
    X64_RegisterRdi = 7,
    X64_RegisterR8 = 8,
    X64_RegisterR9 = 9,
    X64_RegisterR10 = 10,
    X64_RegisterR11 = 11,
    X64_RegisterR12 = 12,
    X64_RegisterR13 = 13,
    X64_RegisterR14 = 14,
    X64_RegisterR15 = 15,
    X64_RegisterRip = 16,
    X64_RegisterRFlags = 17,
    X64_RegisterXmm0 = 18,
    X64_RegisterXmm1 = 19,
    X64_RegisterXmm2 = 20,
    X64_RegisterXmm3 = 21,
    X64_RegisterXmm4 = 22,
    X64_RegisterXmm5 = 23,
    X64_RegisterXmm6 = 24,
    X64_RegisterXmm7 = 25,
    X64_RegisterXmm8 = 26,
    X64_RegisterXmm9 = 27,
    X64_RegisterXmm10 = 28,
    X64_RegisterXmm11 = 29,
    X64_RegisterXmm12 = 30,
    X64_RegisterXmm13 = 31,
    X64_RegisterXmm14 = 32,
    X64_RegisterXmm15 = 33,
    X64_RegisterFpMmx0 = 34,
    X64_RegisterFpMmx1 = 35,
    X64_RegisterFpMmx2 = 36,
    X64_RegisterFpMmx3 = 37,
    X64_RegisterFpMmx4 = 38,
    X64_RegisterFpMmx5 = 39,
    X64_RegisterFpMmx6 = 40,
    X64_RegisterFpMmx7 = 41,
    X64_RegisterFpControlStatus = 42,
    X64_RegisterXmmControlStatus = 43,
    X64_RegisterCr0 = 44,
    X64_RegisterCr2 = 45,
    X64_RegisterCr3 = 46,
    X64_RegisterCr4 = 47,
    X64_RegisterCr8 = 48,
    X64_RegisterEfer = 49,
    X64_RegisterDr0 = 50,
    X64_RegisterDr1 = 51,
    X64_RegisterDr2 = 52,
    X64_RegisterDr3 = 53,
    X64_RegisterDr6 = 54,
    X64_RegisterDr7 = 55,
    X64_RegisterEs = 56,
    X64_RegisterCs = 57,
    X64_RegisterSs = 58,
    X64_RegisterDs = 59,
    X64_RegisterFs = 60,
    X64_RegisterGs = 61,
    X64_RegisterLdtr = 62,
    X64_RegisterTr = 63,
    X64_RegisterIdtr = 64,
    X64_RegisterGdtr = 65,
    X64_RegisterMax = 66,
    ARM64_RegisterX0 = 67,
    ARM64_RegisterX1 = 68,
    ARM64_RegisterX2 = 69,
    ARM64_RegisterX3 = 70,
    ARM64_RegisterX4 = 71,
    ARM64_RegisterX5 = 72,
    ARM64_RegisterX6 = 73,
    ARM64_RegisterX7 = 74,
    ARM64_RegisterX8 = 75,
    ARM64_RegisterX9 = 76,
    ARM64_RegisterX10 = 77,
    ARM64_RegisterX11 = 78,
    ARM64_RegisterX12 = 79,
    ARM64_RegisterX13 = 80,
    ARM64_RegisterX14 = 81,
    ARM64_RegisterX15 = 82,
    ARM64_RegisterX16 = 83,
    ARM64_RegisterX17 = 84,
    ARM64_RegisterX18 = 85,
    ARM64_RegisterX19 = 86,
    ARM64_RegisterX20 = 87,
    ARM64_RegisterX21 = 88,
    ARM64_RegisterX22 = 89,
    ARM64_RegisterX23 = 90,
    ARM64_RegisterX24 = 91,
    ARM64_RegisterX25 = 92,
    ARM64_RegisterX26 = 93,
    ARM64_RegisterX27 = 94,
    ARM64_RegisterX28 = 95,
    ARM64_RegisterXFp = 96,
    ARM64_RegisterXLr = 97,
    ARM64_RegisterPc = 98,
    ARM64_RegisterSpEl0 = 99,
    ARM64_RegisterSpEl1 = 100,
    ARM64_RegisterCpsr = 101,
    ARM64_RegisterQ0 = 102,
    ARM64_RegisterQ1 = 103,
    ARM64_RegisterQ2 = 104,
    ARM64_RegisterQ3 = 105,
    ARM64_RegisterQ4 = 106,
    ARM64_RegisterQ5 = 107,
    ARM64_RegisterQ6 = 108,
    ARM64_RegisterQ7 = 109,
    ARM64_RegisterQ8 = 110,
    ARM64_RegisterQ9 = 111,
    ARM64_RegisterQ10 = 112,
    ARM64_RegisterQ11 = 113,
    ARM64_RegisterQ12 = 114,
    ARM64_RegisterQ13 = 115,
    ARM64_RegisterQ14 = 116,
    ARM64_RegisterQ15 = 117,
    ARM64_RegisterQ16 = 118,
    ARM64_RegisterQ17 = 119,
    ARM64_RegisterQ18 = 120,
    ARM64_RegisterQ19 = 121,
    ARM64_RegisterQ20 = 122,
    ARM64_RegisterQ21 = 123,
    ARM64_RegisterQ22 = 124,
    ARM64_RegisterQ23 = 125,
    ARM64_RegisterQ24 = 126,
    ARM64_RegisterQ25 = 127,
    ARM64_RegisterQ26 = 128,
    ARM64_RegisterQ27 = 129,
    ARM64_RegisterQ28 = 130,
    ARM64_RegisterQ29 = 131,
    ARM64_RegisterQ30 = 132,
    ARM64_RegisterQ31 = 133,
    ARM64_RegisterFpStatus = 134,
    ARM64_RegisterFpControl = 135,
    ARM64_RegisterEsrEl1 = 136,
    ARM64_RegisterSpsrEl1 = 137,
    ARM64_RegisterFarEl1 = 138,
    ARM64_RegisterParEl1 = 139,
    ARM64_RegisterElrEl1 = 140,
    ARM64_RegisterTtbr0El1 = 141,
    ARM64_RegisterTtbr1El1 = 142,
    ARM64_RegisterVbarEl1 = 143,
    ARM64_RegisterSctlrEl1 = 144,
    ARM64_RegisterActlrEl1 = 145,
    ARM64_RegisterTcrEl1 = 146,
    ARM64_RegisterMairEl1 = 147,
    ARM64_RegisterAmairEl1 = 148,
    ARM64_RegisterTpidrEl0 = 149,
    ARM64_RegisterTpidrroEl0 = 150,
    ARM64_RegisterTpidrEl1 = 151,
    ARM64_RegisterContextIdrEl1 = 152,
    ARM64_RegisterCpacrEl1 = 153,
    ARM64_RegisterCsselrEl1 = 154,
    ARM64_RegisterCntkctlEl1 = 155,
    ARM64_RegisterCntvCvalEl0 = 156,
    ARM64_RegisterCntvCtlEl0 = 157,
    ARM64_RegisterMax = 158,
}

#define global X64_RegisterRax              0x0
#define global X64_RegisterRcx              0x1
#define global X64_RegisterRdx              0x2
#define global X64_RegisterRbx              0x3
#define global X64_RegisterRsp              0x4
#define global X64_RegisterRbp              0x5
#define global X64_RegisterRsi              0x6
#define global X64_RegisterRdi              0x7
#define global X64_RegisterR8               0x8
#define global X64_RegisterR9               0x9
#define global X64_RegisterR10              0xA
#define global X64_RegisterR11              0xB
#define global X64_RegisterR12              0xC
#define global X64_RegisterR13              0xD
#define global X64_RegisterR14              0xE
#define global X64_RegisterR15              0xF
#define global X64_RegisterRip              0x10
#define global X64_RegisterRFlags           0x11
#define global X64_RegisterXmm0             0x12
#define global X64_RegisterXmm1             0x13
#define global X64_RegisterXmm2             0x14
#define global X64_RegisterXmm3             0x15
#define global X64_RegisterXmm4             0x16
#define global X64_RegisterXmm5             0x17
#define global X64_RegisterXmm6             0x18
#define global X64_RegisterXmm7             0x19
#define global X64_RegisterXmm8             0x1A
#define global X64_RegisterXmm9             0x1B
#define global X64_RegisterXmm10            0x1C
#define global X64_RegisterXmm11            0x1D
#define global X64_RegisterXmm12            0x1E
#define global X64_RegisterXmm13            0x1F
#define global X64_RegisterXmm14            0x20
#define global X64_RegisterXmm15            0x21
#define global X64_RegisterFpMmx0           0x22
#define global X64_RegisterFpMmx1           0x23
#define global X64_RegisterFpMmx2           0x24
#define global X64_RegisterFpMmx3           0x25
#define global X64_RegisterFpMmx4           0x26
#define global X64_RegisterFpMmx5           0x27
#define global X64_RegisterFpMmx6           0x28
#define global X64_RegisterFpMmx7           0x29
#define global X64_RegisterFpControlStatus  0x2A
#define global X64_RegisterXmmControlStatus 0x2B
#define global X64_RegisterCr0              0x2C
#define global X64_RegisterCr2              0x2D
#define global X64_RegisterCr3              0x2E
#define global X64_RegisterCr4              0x2F
#define global X64_RegisterCr8              0x30
#define global X64_RegisterEfer             0x31
#define global X64_RegisterDr0              0x32
#define global X64_RegisterDr1              0x33
#define global X64_RegisterDr2              0x34
#define global X64_RegisterDr3              0x35
#define global X64_RegisterDr6              0x36
#define global X64_RegisterDr7              0x37
#define global X64_RegisterEs               0x38
#define global X64_RegisterCs               0x39
#define global X64_RegisterSs               0x3A
#define global X64_RegisterDs               0x3B
#define global X64_RegisterFs               0x3C
#define global X64_RegisterGs               0x3D
#define global X64_RegisterLdtr             0x3E
#define global X64_RegisterTr               0x3F
#define global X64_RegisterIdtr             0x40
#define global X64_RegisterGdtr             0x41
#define global X64_RegisterMax              0x42
#define global ARM64_RegisterX0             0x43
#define global ARM64_RegisterX1             0x44
#define global ARM64_RegisterX2             0x45
#define global ARM64_RegisterX3             0x46
#define global ARM64_RegisterX4             0x47
#define global ARM64_RegisterX5             0x48
#define global ARM64_RegisterX6             0x49
#define global ARM64_RegisterX7             0x4A
#define global ARM64_RegisterX8             0x4B
#define global ARM64_RegisterX9             0x4C
#define global ARM64_RegisterX10            0x4D
#define global ARM64_RegisterX11            0x4E
#define global ARM64_RegisterX12            0x4F
#define global ARM64_RegisterX13            0x50
#define global ARM64_RegisterX14            0x51
#define global ARM64_RegisterX15            0x52
#define global ARM64_RegisterX16            0x53
#define global ARM64_RegisterX17            0x54
#define global ARM64_RegisterX18            0x55
#define global ARM64_RegisterX19            0x56
#define global ARM64_RegisterX20            0x57
#define global ARM64_RegisterX21            0x58
#define global ARM64_RegisterX22            0x59
#define global ARM64_RegisterX23            0x5A
#define global ARM64_RegisterX24            0x5B
#define global ARM64_RegisterX25            0x5C
#define global ARM64_RegisterX26            0x5D
#define global ARM64_RegisterX27            0x5E
#define global ARM64_RegisterX28            0x5F
#define global ARM64_RegisterXFp            0x60
#define global ARM64_RegisterXLr            0x61
#define global ARM64_RegisterPc             0x62
#define global ARM64_RegisterSpEl0          0x63
#define global ARM64_RegisterSpEl1          0x64
#define global ARM64_RegisterCpsr           0x65
#define global ARM64_RegisterQ0             0x66
#define global ARM64_RegisterQ1             0x67
#define global ARM64_RegisterQ2             0x68
#define global ARM64_RegisterQ3             0x69
#define global ARM64_RegisterQ4             0x6A
#define global ARM64_RegisterQ5             0x6B
#define global ARM64_RegisterQ6             0x6C
#define global ARM64_RegisterQ7             0x6D
#define global ARM64_RegisterQ8             0x6E
#define global ARM64_RegisterQ9             0x6F
#define global ARM64_RegisterQ10            0x70
#define global ARM64_RegisterQ11            0x71
#define global ARM64_RegisterQ12            0x72
#define global ARM64_RegisterQ13            0x73
#define global ARM64_RegisterQ14            0x74
#define global ARM64_RegisterQ15            0x75
#define global ARM64_RegisterQ16            0x76
#define global ARM64_RegisterQ17            0x77
#define global ARM64_RegisterQ18            0x78
#define global ARM64_RegisterQ19            0x79
#define global ARM64_RegisterQ20            0x7A
#define global ARM64_RegisterQ21            0x7B
#define global ARM64_RegisterQ22            0x7C
#define global ARM64_RegisterQ23            0x7D
#define global ARM64_RegisterQ24            0x7E
#define global ARM64_RegisterQ25            0x7F
#define global ARM64_RegisterQ26            0x80
#define global ARM64_RegisterQ27            0x81
#define global ARM64_RegisterQ28            0x82
#define global ARM64_RegisterQ29            0x83
#define global ARM64_RegisterQ30            0x84
#define global ARM64_RegisterQ31            0x85
#define global ARM64_RegisterFpStatus       0x86
#define global ARM64_RegisterFpControl      0x87
#define global ARM64_RegisterEsrEl1         0x88
#define global ARM64_RegisterSpsrEl1        0x89
#define global ARM64_RegisterFarEl1         0x8A
#define global ARM64_RegisterParEl1         0x8B
#define global ARM64_RegisterElrEl1         0x8C
#define global ARM64_RegisterTtbr0El1       0x8D
#define global ARM64_RegisterTtbr1El1       0x8E
#define global ARM64_RegisterVbarEl1        0x8F
#define global ARM64_RegisterSctlrEl1       0x90
#define global ARM64_RegisterActlrEl1       0x91
#define global ARM64_RegisterTcrEl1         0x92
#define global ARM64_RegisterMairEl1        0x93
#define global ARM64_RegisterAmairEl1       0x94
#define global ARM64_RegisterTpidrEl0       0x95
#define global ARM64_RegisterTpidrroEl0     0x96
#define global ARM64_RegisterTpidrEl1       0x97
#define global ARM64_RegisterContextIdrEl1  0x98
#define global ARM64_RegisterCpacrEl1       0x99
#define global ARM64_RegisterCsselrEl1      0x9A
#define global ARM64_RegisterCntkctlEl1     0x9B
#define global ARM64_RegisterCntvCvalEl0    0x9C
#define global ARM64_RegisterCntvCtlEl0     0x9D
#define global ARM64_RegisterMax            0x9E